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| author | Tristan Gingold <tgingold@free.fr> | 2016-03-15 20:28:56 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2016-03-15 20:28:56 +0100 |
| commit | 37192248646ce7b4688f105877449c640e5039ce (patch) | |
| tree | 9cc7877a5b50d3e48373a39dcbedd7419c5b35c9 /testsuite/gna/bug040/outdata_comp_vpos.vhd | |
| parent | f4a61202e89d2e29416ae9a4b59bea665336c325 (diff) | |
| download | ghdl-37192248646ce7b4688f105877449c640e5039ce.tar.gz ghdl-37192248646ce7b4688f105877449c640e5039ce.tar.bz2 ghdl-37192248646ce7b4688f105877449c640e5039ce.zip | |
Add bug040 testcase.
Diffstat (limited to 'testsuite/gna/bug040/outdata_comp_vpos.vhd')
| -rw-r--r-- | testsuite/gna/bug040/outdata_comp_vpos.vhd | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/testsuite/gna/bug040/outdata_comp_vpos.vhd b/testsuite/gna/bug040/outdata_comp_vpos.vhd new file mode 100644 index 000000000..24dc93183 --- /dev/null +++ b/testsuite/gna/bug040/outdata_comp_vpos.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity outdata_comp_vpos is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(1 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(1 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); +end outdata_comp_vpos; +architecture augh of outdata_comp_vpos is + + -- Embedded RAM + + type ram_type is array (0 to 2) of std_logic_vector(31 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 3 else (others => '-'); + +end architecture; |