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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-03 07:32:06 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-03 07:32:06 +0200 |
| commit | ddbdb98b0ff491bef20bb47668ad1b61a1ac185a (patch) | |
| tree | 2970a8264a26c479d4c075018296aced3682a1dc /testsuite/gna/bug0100/forloop.vhdl | |
| parent | 1a2ea2c583958c0c4c2a227293311f7927c9c2e3 (diff) | |
| download | ghdl-ddbdb98b0ff491bef20bb47668ad1b61a1ac185a.tar.gz ghdl-ddbdb98b0ff491bef20bb47668ad1b61a1ac185a.tar.bz2 ghdl-ddbdb98b0ff491bef20bb47668ad1b61a1ac185a.zip | |
testsuite: add a case for previous commit.
Diffstat (limited to 'testsuite/gna/bug0100/forloop.vhdl')
| -rw-r--r-- | testsuite/gna/bug0100/forloop.vhdl | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/testsuite/gna/bug0100/forloop.vhdl b/testsuite/gna/bug0100/forloop.vhdl new file mode 100644 index 000000000..0c912ec22 --- /dev/null +++ b/testsuite/gna/bug0100/forloop.vhdl @@ -0,0 +1,46 @@ +entity forloop is +end forloop; + +architecture behav of forloop is + signal clk : bit; + signal rst : bit := '1'; + signal tx : bit; + signal data : bit_vector (7 downto 0); + signal valid : bit; + signal err : bit; +begin + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + variable txdata : bit_vector (7 downto 0); + begin + rst <= '1'; + tx <= '1'; + pulse; + rst <= '0'; + + -- Transmit 1 byte. + tx <= '0'; + pulse; + assert err = '0' and valid = '0' severity error; + txdata : + for i in txdata'reverse_range loop + tx <= txdata(i); + pulse; + assert err = '0' and valid = '0' severity error; + end loop; + tx <= '1'; -- parity + pulse; + tx <= '1'; -- stop + pulse; + assert valid = '1' severity error; + assert err = '0' severity error; + assert data = txdata; + wait; + end process; +end behav; |