list: update simulator.

3 files changed, 31 insertions, 30 deletions

diff --git a/src/vhdl/simulate/elaboration.adb b/src/vhdl/simulate/elaboration.adb
index cb777b727..243f9fce9 100644
--- a/src/vhdl/simulate/elaboration.adb
+++ b/src/vhdl/simulate/elaboration.adb
@@ -449,19 +449,16 @@ package body Elaboration is
    -- FIXME: handle pathological cases of recursion.
    -- Due to the rules of analysis, it is not possible to have a circulare
    -- dependence.
-   procedure Elaborate_Dependence (Design_Unit: Iir_Design_Unit) is
-      Depend_List: Iir_Design_Unit_List;
+   procedure Elaborate_Dependence (Design_Unit: Iir_Design_Unit)
+   is
+      Depend_List : constant Iir_List := Get_Dependence_List (Design_Unit);
+      Depend_It : List_Iterator;
       Design: Iir;
       Library_Unit: Iir;
    begin
-      Depend_List := Get_Dependence_List (Design_Unit);
-      if Depend_List = Null_Iir_List then
-         return;
-      end if;
-
-      for I in Natural loop
-         Design := Get_Nth_Element (Depend_List, I);
-         exit when Design = Null_Iir;
+      Depend_It := List_Iterate_Safe (Depend_List);
+      while Is_Valid (Depend_It) loop
+         Design := Get_Element (Depend_It);
          if Get_Kind (Design) = Iir_Kind_Entity_Aspect_Entity then
             --  During Sem, the architecture may be still unknown, and the
             --  dependency is therefore the aspect.
@@ -545,6 +542,7 @@ package body Elaboration is
             when others =>
                Error_Kind ("elaborate_dependence", Library_Unit);
          end case;
+         Next (Depend_It);
       end loop;
    end Elaborate_Dependence;
 
diff --git a/src/vhdl/simulate/simulation-main.adb b/src/vhdl/simulate/simulation-main.adb
index cc46df813..686ec0dc0 100644
--- a/src/vhdl/simulate/simulation-main.adb
+++ b/src/vhdl/simulate/simulation-main.adb
@@ -180,6 +180,7 @@ package body Simulation.Main is
    procedure Elaborate_Drivers (Instance: Block_Instance_Acc; Proc: Iir)
    is
       Driver_List: Iir_List;
+      It : List_Iterator;
       El: Iir;
       Val: Iir_Value_Literal_Acc;
       Marker : Mark_Type;
@@ -193,13 +194,9 @@ package body Simulation.Main is
       Driver_List := Trans_Analyzes.Extract_Drivers (Proc);
 
       -- Some processes have no driver list (assertion).
-      if Driver_List = Null_Iir_List then
-         return;
-      end if;
-
-      for I in Natural loop
-         El := Get_Nth_Element (Driver_List, I);
-         exit when El = Null_Iir;
+      It := List_Iterate_Safe (Driver_List);
+      while Is_Valid (It) loop
+         El := Get_Element (It);
          if Trace_Drivers then
             Put_Line (' ' & Disp_Node (El));
          end if;
@@ -208,6 +205,8 @@ package body Simulation.Main is
          Val := Execute_Name (Instance, El, True);
          Add_Source (Instance, Val, Proc);
          Release (Marker, Expr_Pool);
+
+         Next (It);
       end loop;
    end Elaborate_Drivers;
 
@@ -234,15 +233,17 @@ package body Simulation.Main is
    procedure Register_Sensitivity
      (Instance : Block_Instance_Acc; List : Iir_List)
    is
+      It : List_Iterator;
       Sig : Iir;
       Marker : Mark_Type;
    begin
-      for J in Natural loop
-         Sig := Get_Nth_Element (List, J);
-         exit when Sig = Null_Iir;
+      It := List_Iterate (List);
+      while Is_Valid (It) loop
+         Sig := Get_Element (It);
          Mark (Marker, Expr_Pool);
          Process_Add_Sensitivity (Execute_Name (Instance, Sig, True));
          Release (Marker, Expr_Pool);
+         Next (It);
       end loop;
    end Register_Sensitivity;
 
@@ -847,6 +848,7 @@ package body Simulation.Main is
       end Add_Guard_Sensitivity;
 
       Dep_List : Iir_List;
+      Dep_It : List_Iterator;
       Dep : Iir;
       Data : Guard_Instance_Acc;
    begin
@@ -856,10 +858,11 @@ package body Simulation.Main is
         (To_Ghdl_Value_Ptr (Val_Guard.B1'Address),
          Data.all'Address, Guard_Func'Access);
       Dep_List := Get_Guard_Sensitivity_List (Guard);
-      for I in Natural loop
-         Dep := Get_Nth_Element (Dep_List, I);
-         exit when Dep = Null_Iir;
+      Dep_It := List_Iterate (Dep_List);
+      while Is_Valid (Dep_It) loop
+         Dep := Get_Element (Dep_It);
          Add_Guard_Sensitivity (Execute_Name (Instance, Dep, True));
+         Next (Dep_It);
       end loop;
 
       --  FIXME: free mem
diff --git a/src/vhdl/simulate/simulation.adb b/src/vhdl/simulate/simulation.adb
index 52dc894d2..0d23a20f8 100644
--- a/src/vhdl/simulate/simulation.adb
+++ b/src/vhdl/simulate/simulation.adb
@@ -510,6 +510,7 @@ package body Simulation is
       Expr: Iir;
       El : Iir;
       List: Iir_List;
+      It : List_Iterator;
       Res: Iir_Value_Literal_Acc;
       Status : Boolean;
       Marker : Mark_Type;
@@ -532,13 +533,12 @@ package body Simulation is
          -- occuring on any signal in the sensitivity set of the wait
          -- statement.
          List := Get_Sensitivity_List (Stmt);
-         if List /= Null_Iir_List then
-            for J in Natural loop
-               El := Get_Nth_Element (List, J);
-               exit when El = Null_Iir;
-               Wait_Add_Sensitivity (Execute_Name (Instance, El, True));
-            end loop;
-         end if;
+         It := List_Iterate_Safe (List);
+         while Is_Valid (It) loop
+            El := Get_Element (It);
+            Wait_Add_Sensitivity (Execute_Name (Instance, El, True));
+            Next (It);
+         end loop;
 
          --  LRM93 8.1
          --  It also causes the execution of the corresponding process