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| author | Tristan Gingold <tgingold@free.fr> | 2020-01-10 19:19:38 +0100 | 
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-01-10 19:19:38 +0100 | 
| commit | e17215ff6b3ca865aa09111a15c551e5f0cf1fac (patch) | |
| tree | 63d3cdac91540f36737f8757343c2e0d25fe10fa /src | |
| parent | adaacc8794fbbdb62ba90abe1ba6a53021c84c48 (diff) | |
| download | ghdl-e17215ff6b3ca865aa09111a15c551e5f0cf1fac.tar.gz ghdl-e17215ff6b3ca865aa09111a15c551e5f0cf1fac.tar.bz2 ghdl-e17215ff6b3ca865aa09111a15c551e5f0cf1fac.zip | |
synth: handle ieee.math_real.round  Fix #1075
Diffstat (limited to 'src')
| -rw-r--r-- | src/std_names.adb | 1 | ||||
| -rw-r--r-- | src/std_names.ads | 7 | ||||
| -rw-r--r-- | src/synth/synth-oper.adb | 14 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-math_real.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 1 | 
5 files changed, 22 insertions, 3 deletions
| diff --git a/src/std_names.adb b/src/std_names.adb index 8c97e5f27..d8d71b29b 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -650,6 +650,7 @@ package body Std_Names is        Def ("conv_integer",       Name_Conv_Integer);        Def ("math_real",          Name_Math_Real);        Def ("ceil",               Name_Ceil); +      Def ("round",              Name_Round);        Def ("log2",               Name_Log2);        Def ("sin",                Name_Sin);        Def ("cos",                Name_Cos); diff --git a/src/std_names.ads b/src/std_names.ads index f9cc961a0..efb0ba919 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -731,9 +731,10 @@ package Std_Names is     Name_Conv_Integer       : constant Name_Id := Name_First_Ieee + 032;     Name_Math_Real          : constant Name_Id := Name_First_Ieee + 033;     Name_Ceil               : constant Name_Id := Name_First_Ieee + 034; -   Name_Log2               : constant Name_Id := Name_First_Ieee + 035; -   Name_Sin                : constant Name_Id := Name_First_Ieee + 036; -   Name_Cos                : constant Name_Id := Name_First_Ieee + 037; +   Name_Round              : constant Name_Id := Name_First_Ieee + 035; +   Name_Log2               : constant Name_Id := Name_First_Ieee + 036; +   Name_Sin                : constant Name_Id := Name_First_Ieee + 037; +   Name_Cos                : constant Name_Id := Name_First_Ieee + 038;     Name_Last_Ieee          : constant Name_Id := Name_Cos;     Name_First_Synthesis    : constant Name_Id := Name_Last_Ieee + 1; diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index fcd11201e..471d82979 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -1186,6 +1186,20 @@ package body Synth.Oper is                 return Create_Value_Float                   (Ceil (V.Fp), Get_Value_Type (Syn_Inst, Get_Type (Imp)));              end; +         when Iir_Predefined_Ieee_Math_Real_Round => +            declare +               V : constant Value_Acc := Get_Value (Subprg_Inst, Param1); + +               function Round (Arg : Fp64) return Fp64; +               pragma Import (C, Round); +            begin +               if V.Typ.Kind /= Type_Float then +                  Error_Msg_Synth(+Expr, "argument must be a float value"); +                  return null; +               end if; +               return Create_Value_Float +                 (Round (V.Fp), Get_Value_Type (Syn_Inst, Get_Type (Imp))); +            end;           when Iir_Predefined_Ieee_Math_Real_Sin =>              declare                 V : constant Value_Acc := Get_Value (Subprg_Inst, Param1); diff --git a/src/vhdl/vhdl-ieee-math_real.adb b/src/vhdl/vhdl-ieee-math_real.adb index 1ac5a9b10..d4f83e62c 100644 --- a/src/vhdl/vhdl-ieee-math_real.adb +++ b/src/vhdl/vhdl-ieee-math_real.adb @@ -42,6 +42,8 @@ package body Vhdl.Ieee.Math_Real is                 case Get_Identifier (Decl) is                    when Name_Ceil =>                       Predef := Iir_Predefined_Ieee_Math_Real_Ceil; +                  when Name_Round => +                     Predef := Iir_Predefined_Ieee_Math_Real_Round;                    when Name_Log2 =>                       Predef := Iir_Predefined_Ieee_Math_Real_Log2;                    when Name_Sin => diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 4ed10957d..15e21d738 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5593,6 +5593,7 @@ package Vhdl.Nodes is        --  Math_Real        Iir_Predefined_Ieee_Math_Real_Ceil, +      Iir_Predefined_Ieee_Math_Real_Round,        Iir_Predefined_Ieee_Math_Real_Log2,        Iir_Predefined_Ieee_Math_Real_Sin,        Iir_Predefined_Ieee_Math_Real_Cos, | 
