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| author | Tristan Gingold <tgingold@free.fr> | 2020-05-27 07:26:20 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-05-27 07:26:20 +0200 |
| commit | defe3b033f1c3026312c94e5ce661172c670e9a5 (patch) | |
| tree | ed354ff9a3743e0f756b31afc12aae843a74de82 /src | |
| parent | f5c1bf6aaea852b8bee557bc9de98ce1b65f91ce (diff) | |
| download | ghdl-defe3b033f1c3026312c94e5ce661172c670e9a5.tar.gz ghdl-defe3b033f1c3026312c94e5ce661172c670e9a5.tar.bz2 ghdl-defe3b033f1c3026312c94e5ce661172c670e9a5.zip | |
synth-oper: add support for conv_vector.
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-oper.adb | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 711833f04..a63a0a571 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -1615,7 +1615,8 @@ package body Synth.Oper is (Synth_Sresize (Ctxt, L, Res_Typ.W, Expr), Res_Typ); when Iir_Predefined_Ieee_Numeric_Std_Resize_Uns_Nat - | Iir_Predefined_Ieee_Std_Logic_Arith_Ext => + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Uns + | Iir_Predefined_Ieee_Std_Logic_Arith_Ext => declare W : Width; begin @@ -1645,7 +1646,7 @@ package body Synth.Oper is Create_Vec_Type_By_Length (W, Logic_Type)); end; when Iir_Predefined_Ieee_Numeric_Std_Shf_Left_Uns_Nat - | Iir_Predefined_Ieee_Numeric_Std_Shf_Left_Sgn_Nat => + | Iir_Predefined_Ieee_Numeric_Std_Shf_Left_Sgn_Nat => return Synth_Shift_Rotate (Ctxt, Id_Lsl, L, R, Expr); when Iir_Predefined_Ieee_Numeric_Std_Shf_Right_Uns_Nat => return Synth_Shift_Rotate (Ctxt, Id_Lsr, L, R, Expr); |