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author | Tristan Gingold <tgingold@free.fr> | 2019-07-01 18:22:27 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-07-01 18:22:27 +0200 |
commit | c675324384a2c1b6904e73bf0ed58687479fb351 (patch) | |
tree | 1dd8837d0d7c1def45569501c2089a660eb6ab2d /src | |
parent | 4d37c6d65b6f347000aa7a233efe6c5b0f1cebd5 (diff) | |
download | ghdl-c675324384a2c1b6904e73bf0ed58687479fb351.tar.gz ghdl-c675324384a2c1b6904e73bf0ed58687479fb351.tar.bz2 ghdl-c675324384a2c1b6904e73bf0ed58687479fb351.zip |
synth: improve handling of dynamic slices, add a
Diffstat (limited to 'src')
-rw-r--r-- | src/synth/synth-expr.adb | 33 |
1 files changed, 30 insertions, 3 deletions
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 4dfa7225e..fac2ede6f 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -743,6 +743,10 @@ package body Synth.Expr is return Synth_Compare_Uns_Uns (Id_Eq); when Iir_Predefined_Ieee_Numeric_Std_Lt_Uns_Nat => -- "<" (Unsigned, Natural) + if Is_Const (Right) and then Right.Scal = 0 then + -- Always false. + return Create_Value_Discrete (0); + end if; return Synth_Compare_Uns_Nat (Id_Ult); when Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Slv => -- "<" (Unsigned, Unsigned) [resize] @@ -1006,8 +1010,6 @@ package body Synth.Expr is -- A mul but without any constant value. return; end if; - elsif Get_Id (Get_Module (Inst)) = Id_Uextend then - Inp := Get_Input_Net (Inst, 0); else -- Cannot decompose it. return; @@ -1015,6 +1017,31 @@ package body Synth.Expr is end loop; end Decompose_Mul_Add; + function Is_Same (L, R : Net) return Boolean is + begin + if L = R then + return True; + end if; + + if Get_Width (L) /= Get_Width (R) then + return False; + end if; + + declare + Linst : constant Instance := Get_Parent (L); + Rinst : constant Instance := Get_Parent (R); + begin + if Get_Id (Linst) /= Get_Id (Rinst) then + return False; + end if; + if Get_Id (Linst) = Id_Uextend then + return Is_Same (Get_Input_Net (Linst, 0), + Get_Input_Net (Rinst, 0)); + end if; + end; + return False; + end Is_Same; + procedure Synth_Extract_Dyn_Suffix (Loc : Node; Pfx_Bnd : Value_Bound_Acc; Left : Net; @@ -1045,7 +1072,7 @@ package body Synth.Expr is Decompose_Mul_Add (Right, R_Inp, R_Fac, R_Add); end if; - if L_Inp /= R_Inp then + if not Is_Same (L_Inp, R_Inp) then Error_Msg_Synth (+Loc, "cannot extract same variable part for dynamic slice"); return; |