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author | Tristan Gingold <tgingold@free.fr> | 2017-12-11 06:15:05 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-12-11 06:15:05 +0100 |
commit | b206f4cf1ee63ff517b9be3fcabaf156e07a9a15 (patch) | |
tree | 8bcdd24000cb3f1f886b883b70e0c2404c229bb5 /src | |
parent | 0f42803638b4685ce11f15ef3891505093b3a3f5 (diff) | |
download | ghdl-b206f4cf1ee63ff517b9be3fcabaf156e07a9a15.tar.gz ghdl-b206f4cf1ee63ff517b9be3fcabaf156e07a9a15.tar.bz2 ghdl-b206f4cf1ee63ff517b9be3fcabaf156e07a9a15.zip |
simul-debugger: add debug_upblock.
Diffstat (limited to 'src')
-rw-r--r-- | src/vhdl/simulate/simul-debugger.adb | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/vhdl/simulate/simul-debugger.adb b/src/vhdl/simulate/simul-debugger.adb index 1a3c82245..d2bfcf2b1 100644 --- a/src/vhdl/simulate/simul-debugger.adb +++ b/src/vhdl/simulate/simul-debugger.adb @@ -929,6 +929,12 @@ package body Simul.Debugger is procedure Disp_A_Frame (Instance: Block_Instance_Acc) is begin + if Instance = Global_Instances then + pragma Assert (Instance.Label = Null_Iir); + Put_Line ("global instances"); + return; + end if; + Put (Disp_Node (Instance.Label)); if Instance.Stmt /= Null_Iir then Put (" at "); @@ -949,6 +955,18 @@ package body Simul.Debugger is end Debug_Bt; pragma Unreferenced (Debug_Bt); + procedure Debug_Upblock (Instance : Block_Instance_Acc) + is + Inst : Block_Instance_Acc; + begin + Inst := Instance; + while Inst /= null loop + Disp_A_Frame (Inst); + Inst := Inst.Up_Block; + end loop; + end Debug_Upblock; + pragma Unreferenced (Debug_Upblock); + procedure Disp_Current_Lines is use Files_Map; |