simul: handle psl endpoints (and adjust issue45).

5 files changed, 45 insertions, 17 deletions

diff --git a/src/vhdl/canon.adb b/src/vhdl/canon.adb
index 2657bff1e..72e871d6b 100644
--- a/src/vhdl/canon.adb
+++ b/src/vhdl/canon.adb
@@ -784,7 +784,8 @@ package body Canon is
            | Iir_Kind_Interface_Variable_Declaration
            | Iir_Kind_File_Declaration
            | Iir_Kind_Interface_File_Declaration
-           | Iir_Kind_Object_Alias_Declaration =>
+           | Iir_Kind_Object_Alias_Declaration
+           | Iir_Kind_Psl_Endpoint_Declaration =>
             null;
 
          when Iir_Kind_Enumeration_Literal
diff --git a/src/vhdl/simulate/simul-annotations.adb b/src/vhdl/simulate/simul-annotations.adb
index ba1d8c7ed..1b8182d07 100644
--- a/src/vhdl/simulate/simul-annotations.adb
+++ b/src/vhdl/simulate/simul-annotations.adb
@@ -989,6 +989,8 @@ package body Simul.Annotations is
 
             when Iir_Kind_Psl_Cover_Statement
               | Iir_Kind_Psl_Assert_Statement =>
+               null;
+            when Iir_Kind_Psl_Endpoint_Declaration =>
                Create_Object_Info (Block_Info, El, Kind_PSL);
 
             when Iir_Kind_Simple_Simultaneous_Statement =>
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb
index f2746b69c..e9b4a7b64 100644
--- a/src/vhdl/simulate/simul-elaboration.adb
+++ b/src/vhdl/simulate/simul-elaboration.adb
@@ -874,10 +874,9 @@ package body Simul.Elaboration is
    procedure Elaborate_Type_Range
      (Instance : Block_Instance_Acc; Rc: Iir_Range_Expression)
    is
-      Range_Info : Sim_Info_Acc;
+      Range_Info : constant Sim_Info_Acc := Get_Info (Rc);
       Val : Iir_Value_Literal_Acc;
    begin
-      Range_Info := Get_Info (Rc);
       Create_Object (Instance, Rc);
       Val := Create_Range_Value
         (Execute_Expression (Instance, Get_Left_Limit (Rc)),
@@ -1838,6 +1837,16 @@ package body Simul.Elaboration is
       --  Create the process
       --  Create the finalizer
       PSL_Table.Append (PSL_Entry'(Instance, Stmt, null, False));
+
+      if Get_Kind (Stmt) = Iir_Kind_Psl_Endpoint_Declaration then
+         declare
+            Info : constant Sim_Info_Acc := Get_Info (Stmt);
+         begin
+            Create_Object (Instance, Info.Slot);
+            Instance.Objects (Info.Slot) :=
+              Unshare (Lit_Boolean_False, Instance_Pool);
+         end;
+      end if;
    end Elaborate_Psl_Directive;
 
    --  LRM93 §12.4  Elaboration of a Statement Part.
@@ -1885,7 +1894,8 @@ package body Simul.Elaboration is
                null;
 
             when Iir_Kind_Psl_Cover_Statement
-              | Iir_Kind_Psl_Assert_Statement =>
+              | Iir_Kind_Psl_Assert_Statement
+              | Iir_Kind_Psl_Endpoint_Declaration =>
                Elaborate_Psl_Directive (Instance, Stmt);
 
             when Iir_Kind_Concurrent_Simple_Signal_Assignment =>
diff --git a/src/vhdl/simulate/simul-execution.adb b/src/vhdl/simulate/simul-execution.adb
index 1edcd4da8..ff4887baa 100644
--- a/src/vhdl/simulate/simul-execution.adb
+++ b/src/vhdl/simulate/simul-execution.adb
@@ -2663,7 +2663,8 @@ package body Simul.Execution is
            | Iir_Kind_Attribute_Value
            | Iir_Kind_Iterator_Declaration
            | Iir_Kind_Terminal_Declaration
-           | Iir_Kinds_Quantity_Declaration =>
+           | Iir_Kinds_Quantity_Declaration
+           | Iir_Kind_Psl_Endpoint_Declaration =>
             if Base /= null then
                Res := Base;
             else
@@ -2957,7 +2958,8 @@ package body Simul.Execution is
            | Iir_Kind_Slice_Name
            | Iir_Kind_Selected_Element
            | Iir_Kind_Dereference
-           | Iir_Kind_Implicit_Dereference =>
+           | Iir_Kind_Implicit_Dereference
+           | Iir_Kind_Psl_Endpoint_Declaration =>
             return Execute_Name (Block, Expr);
 
          when Iir_Kinds_Denoting_Name
diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb
index bd51b5b24..ec05895a8 100644
--- a/src/vhdl/simulate/simul-simulation-main.adb
+++ b/src/vhdl/simulate/simul-simulation-main.adb
@@ -27,6 +27,7 @@ with Std_Package;
 with Trans_Analyzes;
 with Simul.Elaboration; use Simul.Elaboration;
 with Simul.Execution; use Simul.Execution;
+with Simul.Annotations; use Simul.Annotations;
 with Ieee.Std_Logic_1164;
 with Grt.Main;
 with Simul.Debugger; use Simul.Debugger;
@@ -429,9 +430,13 @@ package body Simul.Simulation.Main is
       Release (Marker, Expr_Pool);
       if V then
          Nvec := (others => False);
-         if Get_Kind (E.Stmt) = Iir_Kind_Psl_Cover_Statement then
-            Nvec (0) := True;
-         end if;
+         case Get_Kind (E.Stmt) is
+            when Iir_Kind_Psl_Cover_Statement
+              | Iir_Kind_Psl_Endpoint_Declaration =>
+               Nvec (0) := True;
+            when others =>
+               null;
+         end case;
 
          --  For each state: if set, evaluate all outgoing edges.
          NFA := Get_PSL_NFA (E.Stmt);
@@ -466,23 +471,31 @@ package body Simul.Simulation.Main is
          S := Get_Final_State (NFA);
          S_Num := Get_State_Label (S);
          pragma Assert (S_Num = Get_PSL_Nbr_States (E.Stmt) - 1);
-         if Nvec (S_Num) then
-            case Get_Kind (E.Stmt) is
-               when Iir_Kind_Psl_Assert_Statement =>
+         case Get_Kind (E.Stmt) is
+            when Iir_Kind_Psl_Assert_Statement =>
+               if Nvec (S_Num) then
                   Execute_Failed_Assertion
                     (E.Instance, "psl assertion", E.Stmt,
                      "assertion violation", 2);
-               when Iir_Kind_Psl_Cover_Statement =>
+               end if;
+            when Iir_Kind_Psl_Cover_Statement =>
+               if Nvec (S_Num) then
                   if Get_Report_Expression (E.Stmt) /= Null_Iir then
                      Execute_Failed_Assertion
                        (E.Instance, "psl cover", E.Stmt,
                         "sequence covered", 0);
                   end if;
                   E.Done := True;
-               when others =>
-                  Error_Kind ("PSL_Process_Executer", E.Stmt);
-            end case;
-         end if;
+               end if;
+            when Iir_Kind_Psl_Endpoint_Declaration =>
+               declare
+                  Info : constant Sim_Info_Acc := Get_Info (E.Stmt);
+               begin
+                  E.Instance.Objects (Info.Slot).B1 := Ghdl_B1 (Nvec (S_Num));
+               end;
+            when others =>
+               Error_Kind ("PSL_Process_Executer", E.Stmt);
+         end case;
 
          E.States.all := Nvec;
       end if;