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authorTristan Gingold <tgingold@free.fr>2023-01-30 19:01:14 +0100
committerTristan Gingold <tgingold@free.fr>2023-01-30 19:17:28 +0100
commita0321bd7ae81196b1b3a260224b0ee5102c32d61 (patch)
tree085710d7f734b1467b5ed6b554e29c23101a8795 /src
parent4863badab145faf21f31a76997c7bb7274320502 (diff)
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simul-vhdl_elab: fix computation of nbr of sources
Diffstat (limited to 'src')
-rw-r--r--src/simul/simul-vhdl_elab.adb9
1 files changed, 7 insertions, 2 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb
index 49b24b42b..51bed561b 100644
--- a/src/simul/simul-vhdl_elab.adb
+++ b/src/simul/simul-vhdl_elab.adb
@@ -666,6 +666,7 @@ package body Simul.Vhdl_Elab is
end Gather_Process_Sensitivity;
-- Increment the number of sources for EP.
+ -- (Called for actual of an non-in association).
procedure Increment_Nbr_Sources (Ep : Sub_Signal_Type) is
begin
if Ep.Typ.W = 0 then
@@ -1087,7 +1088,10 @@ package body Simul.Vhdl_Elab is
declare
Ns : Nbr_Sources_Type renames E.Nbr_Sources (J - 1);
begin
+ -- Total number of sources. (It was set to 1 to know
+ -- if it is resolved).
Ns.Total := Ns.Nbr_Drivers + Ns.Nbr_Conns;
+ -- Undriven out ports have a default source.
if Ns.Total = 0 and then Is_Out then
Ns.Total := 1;
end if;
@@ -1101,8 +1105,9 @@ package body Simul.Vhdl_Elab is
Signals_Table.Table (E.Collapsed_By)
.Nbr_Sources (J - 1);
begin
- -- Remove 1 for the connection.
- C_Ns.Total := C_Ns.Total + Ns.Total - 1;
+ -- Remove 1 for out connection.
+ C_Ns.Total :=
+ C_Ns.Total + Ns.Total - Boolean'Pos (Is_Out);
end;
end if;
end;