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| author | Tristan Gingold <tgingold@free.fr> | 2023-02-08 11:58:11 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-02-08 16:04:35 +0100 |
| commit | 9dd6b779c2431ad1be462b19474ac351a3501a6d (patch) | |
| tree | 80d6acf7eb042ca5ede1e89292fcba879ed6f02a /src | |
| parent | a465d8c37ea9edda5528bf9f9f160826552eac36 (diff) | |
| download | ghdl-9dd6b779c2431ad1be462b19474ac351a3501a6d.tar.gz ghdl-9dd6b779c2431ad1be462b19474ac351a3501a6d.tar.bz2 ghdl-9dd6b779c2431ad1be462b19474ac351a3501a6d.zip | |
simul: handle signal assignment to procedure individual associations
Diffstat (limited to 'src')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 27 |
1 files changed, 19 insertions, 8 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 5626813a2..d93d13869 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -997,6 +997,22 @@ package body Simul.Vhdl_Simul is procedure Execute_Aggregate_Signal_Assignment is new Assign_Aggregate (Execute_Signal_Assignment); + function Value_To_Sig (Val : Value_Acc) return Memory_Ptr is + begin + case Val.Kind is + when Value_Signal => + declare + E : Signal_Entry renames Signals_Table.Table (Val.S); + begin + return E.Sig; + end; + when Value_Sig_Val => + return Val.I_Sigs; + when others => + raise Internal_Error; + end case; + end Value_To_Sig; + procedure Execute_Signal_Assignment (Inst : Synth_Instance_Acc; Target : Target_Info; Val : Valtyp; @@ -1011,14 +1027,9 @@ package body Simul.Vhdl_Simul is (Inst, Target.Aggr, Target.Targ_Type, Val, Loc); when Target_Simple => - declare - E : Signal_Entry renames - Signals_Table.Table (Target.Obj.Val.S); - begin - Sig := (Target.Targ_Type, - Sig_Index (E.Sig, Target.Off.Net_Off)); - end; - + Sig := (Target.Targ_Type, + Sig_Index (Value_To_Sig (Target.Obj.Val), + Target.Off.Net_Off)); if Val /= No_Valtyp then Mem := Get_Value_Memtyp (Val); else |