diff options
| author | Tristan Gingold <tgingold@free.fr> | 2019-12-24 18:00:24 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-12-24 18:00:24 +0100 |
| commit | 6ffcbcbcf7c34ab6d1f71a73173b0af271892901 (patch) | |
| tree | 7a1e7d9025df590c32171e31913e89541843c229 /src | |
| parent | 1ef6a4011c1c207c7a295148f09b3f403fd87d56 (diff) | |
| download | ghdl-6ffcbcbcf7c34ab6d1f71a73173b0af271892901.tar.gz ghdl-6ffcbcbcf7c34ab6d1f71a73173b0af271892901.tar.bz2 ghdl-6ffcbcbcf7c34ab6d1f71a73173b0af271892901.zip | |
vhdl: recognize ieee.std_logic_1164.is_x.
Diffstat (limited to 'src')
| -rw-r--r-- | src/std_names.adb | 1 | ||||
| -rw-r--r-- | src/std_names.ads | 17 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_1164.adb | 6 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 3 |
4 files changed, 19 insertions, 8 deletions
diff --git a/src/std_names.adb b/src/std_names.adb index 5612363d4..7f6e20242 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -644,6 +644,7 @@ package body Std_Names is Def ("rotate_left", Name_Rotate_Left); Def ("rotate_right", Name_Rotate_Right); Def ("to_bitvector", Name_To_Bitvector); + Def ("is_x", Name_Is_X); Def ("conv_signed", Name_Conv_Signed); Def ("conv_unsigned", Name_Conv_Unsigned); Def ("conv_integer", Name_Conv_Integer); diff --git a/src/std_names.ads b/src/std_names.ads index 57901576b..544f7ed7b 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -725,14 +725,15 @@ package Std_Names is Name_Rotate_Left : constant Name_Id := Name_First_Ieee + 026; Name_Rotate_Right : constant Name_Id := Name_First_Ieee + 027; Name_To_Bitvector : constant Name_Id := Name_First_Ieee + 028; - Name_Conv_Signed : constant Name_Id := Name_First_Ieee + 029; - Name_Conv_Unsigned : constant Name_Id := Name_First_Ieee + 030; - Name_Conv_Integer : constant Name_Id := Name_First_Ieee + 031; - Name_Math_Real : constant Name_Id := Name_First_Ieee + 032; - Name_Ceil : constant Name_Id := Name_First_Ieee + 033; - Name_Log2 : constant Name_Id := Name_First_Ieee + 034; - Name_Sin : constant Name_Id := Name_First_Ieee + 035; - Name_Cos : constant Name_Id := Name_First_Ieee + 036; + Name_Is_X : constant Name_Id := Name_First_Ieee + 029; + Name_Conv_Signed : constant Name_Id := Name_First_Ieee + 030; + Name_Conv_Unsigned : constant Name_Id := Name_First_Ieee + 031; + Name_Conv_Integer : constant Name_Id := Name_First_Ieee + 032; + Name_Math_Real : constant Name_Id := Name_First_Ieee + 033; + Name_Ceil : constant Name_Id := Name_First_Ieee + 034; + Name_Log2 : constant Name_Id := Name_First_Ieee + 035; + Name_Sin : constant Name_Id := Name_First_Ieee + 036; + Name_Cos : constant Name_Id := Name_First_Ieee + 037; Name_Last_Ieee : constant Name_Id := Name_Cos; Name_First_Synthesis : constant Name_Id := Name_Last_Ieee + 1; diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb index 431b5bf6a..9c123d16a 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.adb +++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb @@ -271,6 +271,9 @@ package body Vhdl.Ieee.Std_Logic_1164 is when Name_Op_Condition => Predefined := Iir_Predefined_Ieee_1164_Condition_Operator; + when Name_Is_X => + Predefined := + Iir_Predefined_Ieee_1164_Scalar_Is_X; when others => Predefined := Iir_Predefined_None; end case; @@ -301,6 +304,9 @@ package body Vhdl.Ieee.Std_Logic_1164 is when Name_Or => Predefined := Iir_Predefined_Ieee_1164_Vector_Or_Reduce; + when Name_Is_X => + Predefined := + Iir_Predefined_Ieee_1164_Scalar_Is_X; when others => Predefined := Iir_Predefined_None; end case; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 1f65efb0f..688c30555 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -4920,6 +4920,9 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_1164_To_Bitvector, + Iir_Predefined_Ieee_1164_Vector_Is_X, + Iir_Predefined_Ieee_1164_Scalar_Is_X, + Iir_Predefined_Ieee_1164_Rising_Edge, Iir_Predefined_Ieee_1164_Falling_Edge, |