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author | Tristan Gingold <tgingold@free.fr> | 2019-12-29 18:47:20 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-12-29 18:47:20 +0100 |
commit | 67557e4b9edfe08fc4dfabec790a8301e06762fd (patch) | |
tree | 94c6e41eb9698d2bdef08e316ea37f622ceb8970 /src | |
parent | 24cf373ab40a6bb9b0e9e76556670c1de3fe821d (diff) | |
download | ghdl-67557e4b9edfe08fc4dfabec790a8301e06762fd.tar.gz ghdl-67557e4b9edfe08fc4dfabec790a8301e06762fd.tar.bz2 ghdl-67557e4b9edfe08fc4dfabec790a8301e06762fd.zip |
vhdl-ams: fix overload for simple simultaneous statement.
Fix tree consistency for branch quantity declarations.
Diffstat (limited to 'src')
-rw-r--r-- | src/vhdl/vhdl-nodes.ads | 4 | ||||
-rw-r--r-- | src/vhdl/vhdl-sem_decls.adb | 6 | ||||
-rw-r--r-- | src/vhdl/vhdl-sem_stmts.adb | 20 |
3 files changed, 26 insertions, 4 deletions
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 77aef48b2..33663e01c 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -2185,12 +2185,16 @@ package Vhdl.Nodes is -- -- Get/Set_Tolerance (Field7) -- + -- Set only for the first declaration. -- Get/Set_Plus_Terminal_Name (Field8) -- + -- Set only for the first declaration. -- Get/Set_Minus_Terminal_Name (Field9) -- + -- Same as Plus_Terminal_Name when defined. -- Get/Set_Plus_Terminal (Field10) -- + -- Same as Minus_Terminal_Name when defined. -- Get/Set_Minus_Terminal (Field11) -- -- Get/Set_Has_Identifier_List (Flag3) diff --git a/src/vhdl/vhdl-sem_decls.adb b/src/vhdl/vhdl-sem_decls.adb index 2997e2c26..0ca43ddf1 100644 --- a/src/vhdl/vhdl-sem_decls.adb +++ b/src/vhdl/vhdl-sem_decls.adb @@ -2112,15 +2112,19 @@ package body Vhdl.Sem_Decls is else Is_Second := False; Plus_Name := Sem_Terminal_Name (Plus_Name); + Set_Plus_Terminal_Name (Decl, Plus_Name); + Plus_Name := Strip_Denoting_Name (Plus_Name); Minus_Name := Get_Minus_Terminal_Name (Decl); if Minus_Name /= Null_Iir then Minus_Name := Sem_Terminal_Name (Minus_Name); + Set_Minus_Terminal_Name (Decl, Minus_Name); + Minus_Name := Strip_Denoting_Name (Minus_Name); end if; Value := Get_Default_Value (Decl); end if; Set_Plus_Terminal (Decl, Plus_Name); Set_Minus_Terminal (Decl, Minus_Name); - Plus_Ref := Get_Nature (Get_Named_Entity (Plus_Name)); + Plus_Ref := Get_Nature (Plus_Name); case Iir_Kinds_Branch_Quantity_Declaration (Get_Kind (Decl)) is when Iir_Kind_Across_Quantity_Declaration => Branch_Type := Get_Across_Type (Plus_Ref); diff --git a/src/vhdl/vhdl-sem_stmts.adb b/src/vhdl/vhdl-sem_stmts.adb index 4a420b3a1..e9b14a993 100644 --- a/src/vhdl/vhdl-sem_stmts.adb +++ b/src/vhdl/vhdl-sem_stmts.adb @@ -2112,9 +2112,6 @@ package body Vhdl.Sem_Stmts is return; end if; - Set_Simultaneous_Left (Stmt, Left); - Set_Simultaneous_Right (Stmt, Right); - Res_Type := Search_Compatible_Type (Get_Type (Left), Get_Type (Right)); if Res_Type = Null_Iir then Error_Msg_Sem @@ -2122,6 +2119,23 @@ package body Vhdl.Sem_Stmts is return; end if; + -- AMS-LRM17 11.10 Simple simultaneous statement + -- The base type of each simple expression shall be the same nature + -- type. + if not Sem_Types.Is_Nature_Type (Res_Type) then + Error_Msg_Sem (+Stmt, "type of expressions must be a float types"); + end if; + + if not Is_Expr_Fully_Analyzed (Left) then + Left := Sem_Expression_Ov (Left, Res_Type); + end if; + if not Is_Expr_Fully_Analyzed (Right) then + Right := Sem_Expression_Ov (Right, Res_Type); + end if; + + Set_Simultaneous_Left (Stmt, Left); + Set_Simultaneous_Right (Stmt, Right); + -- FIXME: check for nature type... end Sem_Simple_Simultaneous_Statement; |