diff options
| author | Tristan Gingold <tgingold@free.fr> | 2022-04-27 09:46:49 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-04-27 09:46:49 +0200 |
| commit | 630b01519388cbda2929ccb1928f20806dc8ee17 (patch) | |
| tree | c4b919c079324b7bff30003fd5e5486e7cd92228 /src | |
| parent | 7fdbe576eb04ea5a6015a17caa0b87d8810452fe (diff) | |
| download | ghdl-630b01519388cbda2929ccb1928f20806dc8ee17.tar.gz ghdl-630b01519388cbda2929ccb1928f20806dc8ee17.tar.bz2 ghdl-630b01519388cbda2929ccb1928f20806dc8ee17.zip | |
synth-vhdl_stmts: add implicit conversion for cond assignment
Fix #2042
(The first issue only)
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index f6624b55e..434646f99 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -723,10 +723,15 @@ package body Synth.Vhdl_Stmts is while Ce /= Null_Node loop Val := Synth_Expression_With_Type (C.Inst, Get_Expression (Ce), Targ_Type); + -- Convert to the target subtype so that all the conditional + -- expressions have the same width. + Val := Synth_Subtype_Conversion (Ctxt, Val, Targ_Type, False, Ce); V := Get_Net (Ctxt, Val); Cond := Get_Condition (Ce); if Cond /= Null_Node then Cond_Val := Synth_Expression (C.Inst, Cond); + -- Note: as one input of the mux2 is not connected, there is no + -- check on inputs width. V := Build_Mux2 (Ctxt, Get_Net (Ctxt, Cond_Val), No_Net, V); Set_Location (V, Ce); end if; |