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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-25 06:33:18 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-25 11:43:28 +0200 |
| commit | 548b2ff8d8e1e633853e3e4d25c5a6e0795cb3ee (patch) | |
| tree | e22110ecf9652b137cb3f29aca906e64bd924e5f /src | |
| parent | 09742fc6ac9ec173e82ebd5eb080474cf129ab32 (diff) | |
| download | ghdl-548b2ff8d8e1e633853e3e4d25c5a6e0795cb3ee.tar.gz ghdl-548b2ff8d8e1e633853e3e4d25c5a6e0795cb3ee.tar.bz2 ghdl-548b2ff8d8e1e633853e3e4d25c5a6e0795cb3ee.zip | |
synth: ignore groups and group templates
Diffstat (limited to 'src')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 4 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_decls.adb | 7 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_decls.adb | 5 |
3 files changed, 15 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index ae8b555ec..1185b3cb7 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -304,7 +304,9 @@ package body Simul.Vhdl_Elab is | Iir_Kind_Component_Declaration | Iir_Kind_File_Declaration | Iir_Kind_Protected_Type_Body - | Iir_Kind_Use_Clause => + | Iir_Kind_Use_Clause + | Iir_Kind_Group_Template_Declaration + | Iir_Kind_Group_Declaration => null; when others => Error_Kind ("gather_processes_decl", Decl); diff --git a/src/synth/elab-vhdl_decls.adb b/src/synth/elab-vhdl_decls.adb index eeffc90fd..c1bac611a 100644 --- a/src/synth/elab-vhdl_decls.adb +++ b/src/synth/elab-vhdl_decls.adb @@ -351,6 +351,13 @@ package body Elab.Vhdl_Decls is when Iir_Kinds_Signal_Attribute => -- Not supported by synthesis. null; + when Iir_Kind_Disconnection_Specification => + null; + + when Iir_Kind_Group_Template_Declaration + | Iir_Kind_Group_Declaration => + null; + when others => Vhdl.Errors.Error_Kind ("elab_declaration", Decl); end case; diff --git a/src/synth/synth-vhdl_decls.adb b/src/synth/synth-vhdl_decls.adb index 7bccf96cf..091af79dd 100644 --- a/src/synth/synth-vhdl_decls.adb +++ b/src/synth/synth-vhdl_decls.adb @@ -707,6 +707,10 @@ package body Synth.Vhdl_Decls is when Iir_Kind_Attribute_Implicit_Declaration => -- Not supported by synthesis. null; + when Iir_Kind_Group_Template_Declaration + | Iir_Kind_Group_Declaration => + null; + when Iir_Kind_Suspend_State_Declaration => declare Val : Valtyp; @@ -718,6 +722,7 @@ package body Synth.Vhdl_Decls is Current_Pool := Expr_Pool'Access; Create_Object (Syn_Inst, Decl, Val); end; + when others => Vhdl.Errors.Error_Kind ("synth_declaration", Decl); end case; |