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| author | Tristan Gingold <tgingold@free.fr> | 2020-12-13 20:42:21 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-12-13 20:42:21 +0100 |
| commit | 33ca35119ceb6e15c5b81bc3237a21e1282b46c6 (patch) | |
| tree | 9718067d988ab1f20fd76c4c1092ff7a981f060d /src | |
| parent | 920e4c91bf32a292809f1afa4f96f7ec1312a9c7 (diff) | |
| download | ghdl-33ca35119ceb6e15c5b81bc3237a21e1282b46c6.tar.gz ghdl-33ca35119ceb6e15c5b81bc3237a21e1282b46c6.tar.bz2 ghdl-33ca35119ceb6e15c5b81bc3237a21e1282b46c6.zip | |
synth-oper: handle more conversions. Fix #1536
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-oper.adb | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 8fded25f7..7f70d641c 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -1908,6 +1908,7 @@ package body Synth.Oper is when Iir_Predefined_Ieee_1164_To_Bitvector | Iir_Predefined_Ieee_1164_To_Stdlogicvector_Suv | Iir_Predefined_Ieee_1164_To_Stdlogicvector_Bv + | Iir_Predefined_Ieee_1164_To_Stdulogicvector_Bv | Iir_Predefined_Ieee_Numeric_Std_To_01_Uns | Iir_Predefined_Ieee_Numeric_Std_To_01_Sgn | Iir_Predefined_Ieee_1164_To_X01_Slv => @@ -1917,7 +1918,8 @@ package body Synth.Oper is -- A no-op (with change of bounds). return Create_Value_Net (Get_Net (Ctxt, L), Create_Res_Bound (L)); when Iir_Predefined_Ieee_1164_To_Bit - | Iir_Predefined_Ieee_1164_To_X01_Log => + | Iir_Predefined_Ieee_1164_To_X01_Log + | Iir_Predefined_Ieee_1164_To_Stdulogic => -- A no-op. return Create_Value_Net (Get_Net (Ctxt, L), Res_Typ); |