vhdl-sem_psl: avoid a crash in synth on incorrect clock.

2 files changed, 3 insertions, 0 deletions

diff --git a/src/psl/psl-rewrites.ads b/src/psl/psl-rewrites.ads
index ac76b7805..bb1eb58bc 100644
--- a/src/psl/psl-rewrites.ads
+++ b/src/psl/psl-rewrites.ads
@@ -1,6 +1,7 @@
 with PSL.Nodes; use PSL.Nodes;
 
 package PSL.Rewrites is
+   function Rewrite_Boolean (N : Node) return Node;
    function Rewrite_SERE (N : Node) return Node;
    function Rewrite_Property (N : Node) return Node;
    procedure Rewrite_Unit (N : Node);
diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb
index 0e077b8c9..da5eaa2a2 100644
--- a/src/vhdl/vhdl-sem_psl.adb
+++ b/src/vhdl/vhdl-sem_psl.adb
@@ -24,6 +24,7 @@ with PSL.Types; use PSL.Types;
 with PSL.Nodes; use PSL.Nodes;
 with PSL.Subsets;
 with PSL.Hash;
+with PSL.Rewrites;
 with PSL.Errors; use PSL.Errors;
 
 with Vhdl.Sem_Expr;
@@ -1002,6 +1003,7 @@ package body Vhdl.Sem_Psl is
          Report_End_Group;
       end if;
       Expr := Sem_Boolean (Get_Psl_Boolean (Stmt));
+      Expr := PSL.Rewrites.Rewrite_Boolean (Expr);
       Set_Psl_Boolean (Stmt, Expr);
       Current_Psl_Default_Clock := Stmt;
    end Sem_Psl_Default_Clock;