vhdl: recognize log10 and sqrt from math_real. Fix #2176

4 files changed, 32 insertions, 10 deletions

diff --git a/src/std_names.adb b/src/std_names.adb
index fe0038318..741a464d6 100644
--- a/src/std_names.adb
+++ b/src/std_names.adb
@@ -675,10 +675,12 @@ package body Std_Names is
       Def ("floor",              Name_Floor);
       Def ("round",              Name_Round);
       Def ("log2",               Name_Log2);
+      Def ("log10",              Name_Log10);
       Def ("sin",                Name_Sin);
       Def ("cos",                Name_Cos);
       Def ("arctan",             Name_Arctan);
       Def ("sign",               Name_Sign);
+      Def ("sqrt",               Name_Sqrt);
       Def ("shl",                Name_Shl);
       Def ("shr",                Name_Shr);
       Def ("ext",                Name_Ext);
diff --git a/src/std_names.ads b/src/std_names.ads
index 7b6711c98..97dff6d72 100644
--- a/src/std_names.ads
+++ b/src/std_names.ads
@@ -759,16 +759,18 @@ package Std_Names is
    Name_Floor              : constant Name_Id := Name_First_Ieee_Name + 040;
    Name_Round              : constant Name_Id := Name_First_Ieee_Name + 041;
    Name_Log2               : constant Name_Id := Name_First_Ieee_Name + 042;
-   Name_Sin                : constant Name_Id := Name_First_Ieee_Name + 043;
-   Name_Cos                : constant Name_Id := Name_First_Ieee_Name + 044;
-   Name_Arctan             : constant Name_Id := Name_First_Ieee_Name + 045;
-   Name_Sign               : constant Name_Id := Name_First_Ieee_Name + 046;
-   Name_Shl                : constant Name_Id := Name_First_Ieee_Name + 047;
-   Name_Shr                : constant Name_Id := Name_First_Ieee_Name + 048;
-   Name_Ext                : constant Name_Id := Name_First_Ieee_Name + 049;
-   Name_Sxt                : constant Name_Id := Name_First_Ieee_Name + 050;
-   Name_Find_Leftmost      : constant Name_Id := Name_First_Ieee_Name + 051;
-   Name_Find_Rightmost     : constant Name_Id := Name_First_Ieee_Name + 052;
+   Name_Log10              : constant Name_Id := Name_First_Ieee_Name + 043;
+   Name_Sin                : constant Name_Id := Name_First_Ieee_Name + 044;
+   Name_Cos                : constant Name_Id := Name_First_Ieee_Name + 045;
+   Name_Arctan             : constant Name_Id := Name_First_Ieee_Name + 046;
+   Name_Sign               : constant Name_Id := Name_First_Ieee_Name + 047;
+   Name_Sqrt               : constant Name_Id := Name_First_Ieee_Name + 048;
+   Name_Shl                : constant Name_Id := Name_First_Ieee_Name + 049;
+   Name_Shr                : constant Name_Id := Name_First_Ieee_Name + 050;
+   Name_Ext                : constant Name_Id := Name_First_Ieee_Name + 051;
+   Name_Sxt                : constant Name_Id := Name_First_Ieee_Name + 052;
+   Name_Find_Leftmost      : constant Name_Id := Name_First_Ieee_Name + 053;
+   Name_Find_Rightmost     : constant Name_Id := Name_First_Ieee_Name + 054;
    Name_Last_Ieee_Name     : constant Name_Id := Name_Find_Rightmost;
 
    Name_First_Synthesis    : constant Name_Id := Name_Last_Ieee_Name + 1;
diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb
index 5282473d2..ef685b3f7 100644
--- a/src/synth/synth-vhdl_eval.adb
+++ b/src/synth/synth-vhdl_eval.adb
@@ -2421,6 +2421,13 @@ package body Synth.Vhdl_Eval is
                end if;
                return Create_Memory_Fp64 (Res, Res_Typ);
             end;
+         when Iir_Predefined_Ieee_Math_Real_Sqrt =>
+            declare
+               function Sqrt (Arg : Fp64) return Fp64;
+               pragma Import (C, Sqrt);
+            begin
+               return Create_Memory_Fp64 (Sqrt (Read_Fp64 (Param1)), Res_Typ);
+            end;
          when Iir_Predefined_Ieee_Math_Real_Log2 =>
             declare
                function Log2 (Arg : Fp64) return Fp64;
@@ -2428,6 +2435,13 @@ package body Synth.Vhdl_Eval is
             begin
                return Create_Memory_Fp64 (Log2 (Read_Fp64 (Param1)), Res_Typ);
             end;
+         when Iir_Predefined_Ieee_Math_Real_Log10 =>
+            declare
+               function Log10 (Arg : Fp64) return Fp64;
+               pragma Import (C, Log10);
+            begin
+               return Create_Memory_Fp64 (Log10 (Read_Fp64 (Param1)), Res_Typ);
+            end;
          when Iir_Predefined_Ieee_Math_Real_Ceil =>
             declare
                function Ceil (Arg : Fp64) return Fp64;
diff --git a/src/vhdl/vhdl-ieee-math_real.adb b/src/vhdl/vhdl-ieee-math_real.adb
index d52b8ae85..1bee84826 100644
--- a/src/vhdl/vhdl-ieee-math_real.adb
+++ b/src/vhdl/vhdl-ieee-math_real.adb
@@ -42,6 +42,8 @@ package body Vhdl.Ieee.Math_Real is
                case Get_Identifier (Decl) is
                   when Name_Sign =>
                      Def := Iir_Predefined_Ieee_Math_Real_Sign;
+                  when Name_Sqrt =>
+                     Def := Iir_Predefined_Ieee_Math_Real_Sqrt;
                   when Name_Mod =>
                      Def := Iir_Predefined_Ieee_Math_Real_Mod;
                   when Name_Ceil =>
@@ -52,6 +54,8 @@ package body Vhdl.Ieee.Math_Real is
                      Def := Iir_Predefined_Ieee_Math_Real_Round;
                   when Name_Log2 =>
                      Def := Iir_Predefined_Ieee_Math_Real_Log2;
+                  when Name_Log10 =>
+                     Def := Iir_Predefined_Ieee_Math_Real_Log10;
                   when Name_Sin =>
                      Def := Iir_Predefined_Ieee_Math_Real_Sin;
                   when Name_Cos =>