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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-26 20:12:18 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-26 20:12:18 +0200 |
| commit | 0f0babe5e0cbf7eb6ed6926786f36b3d9a42ece9 (patch) | |
| tree | 3373c9cf61bf76c3f2d75d48367c2e9f2d700d58 /src | |
| parent | e7ffd3ed6229d70b38b1cbff02be19766aa94419 (diff) | |
| download | ghdl-0f0babe5e0cbf7eb6ed6926786f36b3d9a42ece9.tar.gz ghdl-0f0babe5e0cbf7eb6ed6926786f36b3d9a42ece9.tar.bz2 ghdl-0f0babe5e0cbf7eb6ed6926786f36b3d9a42ece9.zip | |
synth-vhdl_eval: handle nor, nand
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-vhdl_eval.adb | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb index f316f19e7..f64be7158 100644 --- a/src/synth/synth-vhdl_eval.adb +++ b/src/synth/synth-vhdl_eval.adb @@ -432,6 +432,13 @@ package body Synth.Vhdl_Eval is when Iir_Predefined_Error => return Null_Memtyp; + when Iir_Predefined_Boolean_Or + | Iir_Predefined_Bit_Or + | Iir_Predefined_Boolean_And + | Iir_Predefined_Bit_And => + -- Short-circuit operators. + raise Internal_Error; + when Iir_Predefined_Boolean_Xor | Iir_Predefined_Bit_Xor => return Create_Memory_U8 @@ -439,6 +446,20 @@ package body Synth.Vhdl_Eval is xor Boolean'Val (Read_Discrete (Right))), Res_Typ); + when Iir_Predefined_Boolean_Nand + | Iir_Predefined_Bit_Nand => + return Create_Memory_U8 + (Boolean'Pos (not (Boolean'Val (Read_Discrete (Left)) + and Boolean'Val (Read_Discrete (Right)))), + Res_Typ); + + when Iir_Predefined_Boolean_Nor + | Iir_Predefined_Bit_Nor => + return Create_Memory_U8 + (Boolean'Pos (not (Boolean'Val (Read_Discrete (Left)) + or Boolean'Val (Read_Discrete (Right)))), + Res_Typ); + when Iir_Predefined_Integer_Plus | Iir_Predefined_Physical_Plus => declare |