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| author | Tristan Gingold <tgingold@free.fr> | 2020-04-11 07:55:43 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-04-11 07:55:43 +0200 |
| commit | 06ee1499b50458cd23118b99b3727f8a08d847bd (patch) | |
| tree | a907228fe0adafa7213f222fbbee96209e02c6f1 /src | |
| parent | ba140c09d7b9f21cbccdd29e1fdda67e110a38f0 (diff) | |
| download | ghdl-06ee1499b50458cd23118b99b3727f8a08d847bd.tar.gz ghdl-06ee1499b50458cd23118b99b3727f8a08d847bd.tar.bz2 ghdl-06ee1499b50458cd23118b99b3727f8a08d847bd.zip | |
vhdl: recognize ext/sxt from std_logic_arith.
Diffstat (limited to 'src')
| -rw-r--r-- | src/std_names.adb | 2 | ||||
| -rw-r--r-- | src/std_names.ads | 4 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_arith.adb | 10 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 3 |
4 files changed, 18 insertions, 1 deletions
diff --git a/src/std_names.adb b/src/std_names.adb index 9d9cfcbe7..ece86763f 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -668,6 +668,8 @@ package body Std_Names is Def ("log2", Name_Log2); Def ("sin", Name_Sin); Def ("cos", Name_Cos); + Def ("ext", Name_Ext); + Def ("sxt", Name_Sxt); Def ("allconst", Name_Allconst); Def ("allseq", Name_Allseq); diff --git a/src/std_names.ads b/src/std_names.ads index 2c12c0f00..6ed7fb6d5 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -751,7 +751,9 @@ package Std_Names is Name_Log2 : constant Name_Id := Name_First_Ieee_Name + 038; Name_Sin : constant Name_Id := Name_First_Ieee_Name + 039; Name_Cos : constant Name_Id := Name_First_Ieee_Name + 040; - Name_Last_Ieee_Name : constant Name_Id := Name_Cos; + Name_Ext : constant Name_Id := Name_First_Ieee_Name + 041; + Name_Sxt : constant Name_Id := Name_First_Ieee_Name + 042; + Name_Last_Ieee_Name : constant Name_Id := Name_Sxt; Name_First_Synthesis : constant Name_Id := Name_Last_Ieee_Name + 1; Name_Allconst : constant Name_Id := Name_First_Synthesis + 000; diff --git a/src/vhdl/vhdl-ieee-std_logic_arith.adb b/src/vhdl/vhdl-ieee-std_logic_arith.adb index 4c2b517ec..c1d7caccf 100644 --- a/src/vhdl/vhdl-ieee-std_logic_arith.adb +++ b/src/vhdl/vhdl-ieee-std_logic_arith.adb @@ -397,6 +397,16 @@ package body Vhdl.Ieee.Std_Logic_Arith is Def := Handle_Cmp (Eq_Patterns); when Name_Op_Inequality => Def := Handle_Cmp (Ne_Patterns); + when Name_Ext => + if Arg1_Kind /= Type_Slv or Arg2_Kind /= Type_Int then + raise Error; + end if; + Def := Iir_Predefined_Ieee_Std_Logic_Arith_Ext; + when Name_Sxt => + if Arg1_Kind /= Type_Slv or Arg2_Kind /= Type_Int then + raise Error; + end if; + Def := Iir_Predefined_Ieee_Std_Logic_Arith_Sxt; when others => null; end case; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index c6f7d0891..393780a3f 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5782,6 +5782,9 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Sgn, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Log, + Iir_Predefined_Ieee_Std_Logic_Arith_Ext, + Iir_Predefined_Ieee_Std_Logic_Arith_Sxt, + Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Uns_Uns, Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Sgn, Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Sgn, |