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| author | Tristan Gingold <tgingold@free.fr> | 2019-12-31 12:26:21 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-12-31 18:57:44 +0100 |
| commit | 03e71f74ace9dbd543435b5f94df87b83bb7d54f (patch) | |
| tree | d34cb1a5e9d9f10b56705decc58ebf1d049e9b6a /src | |
| parent | ba0bcbe24ecec931358c0cf230841d3c86ffc8bb (diff) | |
| download | ghdl-03e71f74ace9dbd543435b5f94df87b83bb7d54f.tar.gz ghdl-03e71f74ace9dbd543435b5f94df87b83bb7d54f.tar.bz2 ghdl-03e71f74ace9dbd543435b5f94df87b83bb7d54f.zip | |
netlists-disp_vhdl: display iadff.
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 7 | ||||
| -rw-r--r-- | src/synth/netlists-gates.ads | 19 |
2 files changed, 19 insertions, 7 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 29fc6f169..41c32eeaa 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -882,7 +882,8 @@ package body Netlists.Disp_Vhdl is Put_Line (";"); when Id_Const_Bit => null; - when Id_Adff => + when Id_Adff + | Id_Iadff => Disp_Template (" process (\i0, \i2)" & NL & " begin" & NL & " if \i2 = '1' then" & NL & @@ -1153,6 +1154,10 @@ package body Netlists.Disp_Vhdl is Put (" := "); Disp_Constant_Inline (Get_Net_Parent (Get_Input_Net (Inst, 2))); + when Id_Iadff => + Put (" := "); + Disp_Constant_Inline + (Get_Net_Parent (Get_Input_Net (Inst, 4))); when Constant_Module_Id => Put (" := "); Disp_Constant_Inline (Inst); diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads index 1c1f08c22..e185ee085 100644 --- a/src/synth/netlists-gates.ads +++ b/src/synth/netlists-gates.ads @@ -130,16 +130,23 @@ package Netlists.Gates is -- 1: D -- 2: RST -- 3: RST_VAL - -- Output: Q + -- Output: 0: Q Id_Adff : constant Module_Id := 51; -- A simple DFF with an initial value (must be constant). This is -- for FPGAs. - -- Input 0: Clock - -- Input 1: Data + -- Inputs: 0: CLK + -- 1: D + -- 2: INIT (initial value) + -- Output: 0: Q Id_Idff : constant Module_Id := 52; -- A DFF with an asynchronous reset and an initial value. - -- Input 2: Initial value. + -- Inputs: 0: CLK + -- 1: D + -- 2: RST + -- 3: RST_VAL + -- 4: INIT (initial value) + -- Output: 0: Q Id_Iadff : constant Module_Id := 53; -- Width change: truncate or extend. Sign is know in order to possibly @@ -157,8 +164,8 @@ package Netlists.Gates is Id_Extract : constant Module_Id := 68; -- OUT := IN0[IN1+OFF+WD-1:IN1+OFF] - -- Input0: the memory - -- Input1: then index + -- Inputs: MEM (the memory) + -- IDX (then index) -- Param0: offset Id_Dyn_Extract : constant Module_Id := 69; |