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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-15 03:13:23 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-15 03:13:23 +0200 |
| commit | 8ada97528f410837465f61128fadda39d2c854ee (patch) | |
| tree | 5425f6ca45b2ff79db28aaa3d9eb159ad580d07f /src/vhdl | |
| parent | 05570966dd67fa303302bfb3664b7027fea9084c (diff) | |
| download | ghdl-8ada97528f410837465f61128fadda39d2c854ee.tar.gz ghdl-8ada97528f410837465f61128fadda39d2c854ee.tar.bz2 ghdl-8ada97528f410837465f61128fadda39d2c854ee.zip | |
synth: handle access subtypes
Diffstat (limited to 'src/vhdl')
| -rw-r--r-- | src/vhdl/vhdl-annotations.adb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index 77cc58434..1bb0bff82 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -401,7 +401,7 @@ package body Vhdl.Annotations is end if; when Iir_Kind_Access_Subtype_Definition => - null; + Create_Object_Info (Block_Info, Def, Kind_Type); when Iir_Kind_File_Type_Definition => if Flag_Synthesis then |