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author | Tristan Gingold <tgingold@free.fr> | 2017-12-18 19:12:57 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-12-20 20:58:40 +0100 |
commit | 6bc6e9b69843f897bf43002c8da58e513db7b6e3 (patch) | |
tree | 894d8ec73c06f977dba69975a3cf472af7b4bb8e /src/vhdl | |
parent | 9db20e133d5c47f8d54710c2676792337cc94f54 (diff) | |
download | ghdl-6bc6e9b69843f897bf43002c8da58e513db7b6e3.tar.gz ghdl-6bc6e9b69843f897bf43002c8da58e513db7b6e3.tar.bz2 ghdl-6bc6e9b69843f897bf43002c8da58e513db7b6e3.zip |
grt: reorganize simulation loop.
Diffstat (limited to 'src/vhdl')
-rw-r--r-- | src/vhdl/simulate/simul-simulation-main.adb | 23 |
1 files changed, 21 insertions, 2 deletions
diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb index 34041f645..a83f0988e 100644 --- a/src/vhdl/simulate/simul-simulation-main.adb +++ b/src/vhdl/simulate/simul-simulation-main.adb @@ -1125,7 +1125,10 @@ package body Simul.Simulation.Main is end if; end Ghdl_Elaborate; - procedure Simulation_Entity (Top_Conf : Iir_Design_Unit) is + procedure Simulation_Entity (Top_Conf : Iir_Design_Unit) + is + Stop : Boolean; + Status : Integer; begin Top_Config := Top_Conf; @@ -1135,7 +1138,23 @@ package body Simul.Simulation.Main is Debug (Reason_Start); end if; - Grt.Main.Run; + Grt.Main.Run_Elab (Stop); + if Stop then + return; + end if; + + Grt.Processes.Simulation_Init; + + Status := Grt.Main.Run_Through_Longjump + (Grt.Processes.Simulation_Main_Loop'Access); + + if Status = Grt.Errors.Run_Limit then + Grt.Processes.Simulation_Explain_Limit; + end if; + + Grt.Processes.Simulation_Finish; + + Grt.Main.Run_Finish (Status); exception when Debugger_Quit => null; |