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| author | Tristan Gingold <tgingold@free.fr> | 2020-06-19 06:43:48 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-06-19 06:44:43 +0200 |
| commit | 5f4992cf1b8cd862b5b1cde498e2a7a867439b5a (patch) | |
| tree | 47614b19a3231b96a7c88c0bcb2d37614a6381fd /src/vhdl | |
| parent | 8ea10774e2643e653dc6b5a07a6abd43fd01055d (diff) | |
| download | ghdl-5f4992cf1b8cd862b5b1cde498e2a7a867439b5a.tar.gz ghdl-5f4992cf1b8cd862b5b1cde498e2a7a867439b5a.tar.bz2 ghdl-5f4992cf1b8cd862b5b1cde498e2a7a867439b5a.zip | |
vhdl: decode to_x01 (from ieee.std_logic_1164)
Diffstat (limited to 'src/vhdl')
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_1164.adb | 7 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 21 |
2 files changed, 28 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb index bb4b12bce..44fc5f631 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.adb +++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb @@ -322,6 +322,13 @@ package body Vhdl.Ieee.Std_Logic_1164 is Predefined := Iir_Predefined_Ieee_1164_To_Stdulogicvector_Bv; end if; + when Name_To_X01 => + if Is_Vector_Function (Decl) then + -- TODO: distinguish slv/suv. + Predefined := Iir_Predefined_Ieee_1164_To_X01_Slv; + elsif Is_Scalar_Function (Decl) then + Predefined := Iir_Predefined_Ieee_1164_To_X01_Log; + end if; when others => if Is_Scalar_Scalar_Function (Decl) then case Get_Identifier (Decl) is diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 97eeccf24..07faf5b7b 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5500,6 +5500,27 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_1164_To_Stdulogicvector_Bv, Iir_Predefined_Ieee_1164_To_Stdulogicvector_Slv, + Iir_Predefined_Ieee_1164_To_X01_Slv, + Iir_Predefined_Ieee_1164_To_X01_Suv, + Iir_Predefined_Ieee_1164_To_X01_Log, + Iir_Predefined_Ieee_1164_To_X01_Bv_Slv, + Iir_Predefined_Ieee_1164_To_X01_Bv_Suv, + Iir_Predefined_Ieee_1164_To_X01_Bit_Log, + + Iir_Predefined_Ieee_1164_To_X01Z_Slv, + Iir_Predefined_Ieee_1164_To_X01Z_Suv, + Iir_Predefined_Ieee_1164_To_X01Z_Log, + Iir_Predefined_Ieee_1164_To_X01Z_Bv_Slv, + Iir_Predefined_Ieee_1164_To_X01Z_Bv_Suv, + Iir_Predefined_Ieee_1164_To_X01Z_Bit_Log, + + Iir_Predefined_Ieee_1164_To_UX01_Slv, + Iir_Predefined_Ieee_1164_To_UX01_Suv, + Iir_Predefined_Ieee_1164_To_UX01_Log, + Iir_Predefined_Ieee_1164_To_UX01_Bv_Slv, + Iir_Predefined_Ieee_1164_To_UX01_Bv_Suv, + Iir_Predefined_Ieee_1164_To_UX01_Bit_Log, + Iir_Predefined_Ieee_1164_Vector_Is_X, Iir_Predefined_Ieee_1164_Scalar_Is_X, |