diff options
author | Tristan Gingold <tgingold@free.fr> | 2020-06-01 19:41:46 +0200 |
---|---|---|
committer | Tristan Gingold <tgingold@free.fr> | 2020-06-02 03:24:53 +0200 |
commit | d667339603a7a3e408b135737b058e2a9976ae44 (patch) | |
tree | a50f0d2179cef4741555396a1fb57b42a6b152bf /src/vhdl/vhdl-nodes.ads | |
parent | 21af50dafb4f0fa27a6d8757e3953f310d0e3e8f (diff) | |
download | ghdl-d667339603a7a3e408b135737b058e2a9976ae44.tar.gz ghdl-d667339603a7a3e408b135737b058e2a9976ae44.tar.bz2 ghdl-d667339603a7a3e408b135737b058e2a9976ae44.zip |
Synthesis of PSL prev function.
Diffstat (limited to 'src/vhdl/vhdl-nodes.ads')
-rw-r--r-- | src/vhdl/vhdl-nodes.ads | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 0965b5388..05cbcf576 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -856,8 +856,10 @@ package Vhdl.Nodes is -- -- Get/Set_Clock_Expression (Field4) -- - -- Reference to the clock node (can be the default one). - -- Get/Set_Clock (Field3) + -- Reference to the default_clock node. + -- Get/Set_Default_Clock (Field3) + -- + -- Get/Set_Expr_Staticness (State1) -- Iir_Kind_Psl_Stable (Short) -- Iir_Kind_Psl_Rose (Short) @@ -869,8 +871,10 @@ package Vhdl.Nodes is -- -- Get/Set_Clock_Expression (Field4) -- - -- Reference to the clock node (can be the default one). - -- Get/Set_Clock (Field3) + -- Reference to the defult_clock node. + -- Get/Set_Default_Clock (Field3) + -- + -- Get/Set_Expr_Staticness (State1) -- Iir_Kind_Signature (Medium) -- @@ -8992,8 +8996,8 @@ package Vhdl.Nodes is function Get_Clock_Expression (N : Iir) return Iir; procedure Set_Clock_Expression (N : Iir; Clk : Iir); - -- Reference to the clock node (can be the default one). + -- Reference to the default_clock node. -- Field: Field3 Ref - function Get_Clock (N : Iir) return Iir; - procedure Set_Clock (N : Iir; Clk : Iir); + function Get_Default_Clock (N : Iir) return Iir; + procedure Set_Default_Clock (N : Iir; Clk : Iir); end Vhdl.Nodes; |