Add support for --time-resolution (jit only). Fix #613

5 files changed, 18 insertions, 22 deletions

diff --git a/src/vhdl/translate/ortho_front.adb b/src/vhdl/translate/ortho_front.adb
index 236c94906..143a6f6f1 100644
--- a/src/vhdl/translate/ortho_front.adb
+++ b/src/vhdl/translate/ortho_front.adb
@@ -393,6 +393,7 @@ package body Ortho_Front is
       Res : Iir_Design_File;
       Design : Iir_Design_Unit;
       Next_Design : Iir_Design_Unit;
+      Config : Iir;
    begin
       if Nbr_Parse = 0 then
          --  Initialize only once...
@@ -417,9 +418,13 @@ package body Ortho_Front is
                Error_Msg_Option ("missing -l for --elab");
                raise Option_Error;
             end if;
-            Translation.Elaborate
-              (Elab_Entity.all, Elab_Architecture.all,
-               Elab_Filelist.all, False);
+            Config := Configuration.Configure
+              (Elab_Entity.all, Elab_Architecture.all);
+            if Errorout.Nbr_Errors > 0 then
+               --  This may happen (bad entity for example).
+               raise Compilation_Error;
+            end if;
+            Translation.Elaborate (Config, Elab_Filelist.all, False);
 
             if Errorout.Nbr_Errors > 0 then
                --  This may happen (bad entity for example).
@@ -464,8 +469,9 @@ package body Ortho_Front is
 
             Flags.Flag_Elaborate := True;
             Flags.Flag_Only_Elab_Warnings := False;
-            Translation.Elaborate
-              (Elab_Entity.all, Elab_Architecture.all, "", True);
+            Config := Configuration.Configure
+              (Elab_Entity.all, Elab_Architecture.all);
+            Translation.Elaborate (Config, "", True);
 
             if Errorout.Nbr_Errors > 0 then
                --  This may happen (bad entity for example).
diff --git a/src/vhdl/translate/trans-chap12.adb b/src/vhdl/translate/trans-chap12.adb
index b0e096565..9a2d7022e 100644
--- a/src/vhdl/translate/trans-chap12.adb
+++ b/src/vhdl/translate/trans-chap12.adb
@@ -587,8 +587,7 @@ package body Trans.Chap12 is
       R := fclose (F);
    end Write_File_List;
 
-   procedure Elaborate (Primary : String;
-                        Secondary : String;
+   procedure Elaborate (Config : Iir_Design_Unit;
                         Filelist : String;
                         Whole : Boolean)
    is
@@ -596,17 +595,12 @@ package body Trans.Chap12 is
 
       Unit : Iir_Design_Unit;
       Lib_Unit : Iir;
-      Config : Iir_Design_Unit;
       Config_Lib : Iir_Configuration_Declaration;
       Entity : Iir_Entity_Declaration;
       Arch : Iir_Architecture_Body;
       Conf_Info : Config_Info_Acc;
       Last_Design_Unit : Natural;
    begin
-      Config := Configure (Primary, Secondary);
-      if Config = Null_Iir then
-         return;
-      end if;
       Config_Lib := Get_Library_Unit (Config);
       Entity := Get_Entity (Config_Lib);
       Arch := Strip_Denoting_Name
diff --git a/src/vhdl/translate/trans-chap12.ads b/src/vhdl/translate/trans-chap12.ads
index 23abea998..a0db62399 100644
--- a/src/vhdl/translate/trans-chap12.ads
+++ b/src/vhdl/translate/trans-chap12.ads
@@ -26,10 +26,8 @@ package Trans.Chap12 is
    --  Write to file FILELIST all the files that are needed to link the design.
    procedure Write_File_List (Filelist : String);
 
-   --  Primary unit + secondary unit (architecture name which may be null)
-   --  to elaborate.
-   procedure Elaborate (Primary : String;
-                        Secondary : String;
+   --  Generate elaboration code for CONFIG.
+   procedure Elaborate (Config : Iir_Design_Unit;
                         Filelist : String;
                         Whole : Boolean);
 end Trans.Chap12;
diff --git a/src/vhdl/translate/translation.adb b/src/vhdl/translate/translation.adb
index 5c39283e3..a7ec6e7da 100644
--- a/src/vhdl/translate/translation.adb
+++ b/src/vhdl/translate/translation.adb
@@ -2085,8 +2085,7 @@ package body Translation is
       Free_Old_Temp;
    end Finalize;
 
-   procedure Elaborate (Primary : String;
-                        Secondary : String;
+   procedure Elaborate (Config : Iir;
                         Filelist : String;
                         Whole : Boolean) renames Trans.Chap12.Elaborate;
 
diff --git a/src/vhdl/translate/translation.ads b/src/vhdl/translate/translation.ads
index 2228f8973..4c9b2ff27 100644
--- a/src/vhdl/translate/translation.ads
+++ b/src/vhdl/translate/translation.ads
@@ -40,10 +40,9 @@ package Translation is
 
    procedure Gen_Filename (Design_File : Iir);
 
-   --  Primary unit + secondary unit (architecture name which may be null)
-   --  to elaborate.
-   procedure Elaborate (Primary : String;
-                        Secondary : String;
+   --  Generate elaboration code for CONFIG.  Also use units from Configure
+   --  package.
+   procedure Elaborate (Config : Iir;
                         Filelist : String;
                         Whole : Boolean);