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| author | Tristan Gingold <tgingold@free.fr> | 2018-11-14 18:35:41 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2018-11-14 18:35:41 +0100 |
| commit | b6c523106ab498375a7874923742c6b806700a9a (patch) | |
| tree | 83f21964f8290a845a9acaba325056f5a420a963 /src/vhdl/translate | |
| parent | 12ea165c7474ad0a7a486062f816071378492eed (diff) | |
| download | ghdl-b6c523106ab498375a7874923742c6b806700a9a.tar.gz ghdl-b6c523106ab498375a7874923742c6b806700a9a.tar.bz2 ghdl-b6c523106ab498375a7874923742c6b806700a9a.zip | |
Create sem_lib from libraries.
Diffstat (limited to 'src/vhdl/translate')
| -rw-r--r-- | src/vhdl/translate/ortho_front.adb | 7 | ||||
| -rw-r--r-- | src/vhdl/translate/trans-chap12.adb | 5 |
2 files changed, 7 insertions, 5 deletions
diff --git a/src/vhdl/translate/ortho_front.adb b/src/vhdl/translate/ortho_front.adb index 8e0532738..d7dee0015 100644 --- a/src/vhdl/translate/ortho_front.adb +++ b/src/vhdl/translate/ortho_front.adb @@ -25,6 +25,7 @@ with Flags; with Configuration; with Translation; with Sem; +with Sem_Lib; use Sem_Lib; with Errorout; use Errorout; with GNAT.OS_Lib; with Bug; @@ -268,7 +269,7 @@ package body Ortho_Front is Flags.Flag_Elaborate := False; -- Read and parse the file. - Res := Libraries.Load_File (Vhdl_File); + Res := Load_File (Vhdl_File); if Errorout.Nbr_Errors > 0 then raise Compilation_Error; end if; @@ -279,7 +280,7 @@ package body Ortho_Front is Design := Get_First_Design_Unit (Res); while Is_Valid (Design) loop -- Analyze and canon a design unit. - Libraries.Finish_Compilation (Design, True); + Finish_Compilation (Design, True); Next_Design := Get_Chain (Design); if Errorout.Nbr_Errors = 0 then @@ -449,7 +450,7 @@ package body Ortho_Front is begin L := Anaelab_Files; while L /= null loop - Res := Libraries.Load_File (L.Id); + Res := Load_File (L.Id); if Errorout.Nbr_Errors > 0 then raise Compilation_Error; end if; diff --git a/src/vhdl/translate/trans-chap12.adb b/src/vhdl/translate/trans-chap12.adb index dfd50856c..2f8884841 100644 --- a/src/vhdl/translate/trans-chap12.adb +++ b/src/vhdl/translate/trans-chap12.adb @@ -26,6 +26,7 @@ with Name_Table; with Libraries; with Flags; with Sem; +with Sem_Lib; use Sem_Lib; with Trans.Chap1; with Trans.Chap2; with Trans.Chap6; @@ -360,7 +361,7 @@ package body Trans.Chap12 is Decl : Iir; begin - Libraries.Load_Design_Unit (Unit, Null_Iir); + Load_Design_Unit (Unit, Null_Iir); Pkg := Get_Library_Unit (Unit); Reset_Identifier_Prefix; Lib := Get_Library (Get_Design_File (Get_Design_Unit (Pkg))); @@ -434,7 +435,7 @@ package body Trans.Chap12 is Lib_Unit : Iir; begin -- Load the unit in memory to compute the dependence list. - Libraries.Load_Design_Unit (Unit, Null_Iir); + Load_Design_Unit (Unit, Null_Iir); Update_Node_Infos; Set_Elab_Flag (Unit, True); |