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| author | Tristan Gingold <tgingold@free.fr> | 2019-05-05 08:00:35 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-05-05 08:05:12 +0200 |
| commit | 3fa8d9eb8b700044d149bdf12da6cb023568b8c0 (patch) | |
| tree | 3cbd54423bad53e6db401e43ef0e4216833cd8b9 /src/vhdl/translate | |
| parent | 85d360929d13e6b0bcb082f144883a43f402ce22 (diff) | |
| download | ghdl-3fa8d9eb8b700044d149bdf12da6cb023568b8c0.tar.gz ghdl-3fa8d9eb8b700044d149bdf12da6cb023568b8c0.tar.bz2 ghdl-3fa8d9eb8b700044d149bdf12da6cb023568b8c0.zip | |
vhdl: move ieee packages to vhdl children.
Diffstat (limited to 'src/vhdl/translate')
| -rw-r--r-- | src/vhdl/translate/ortho_front.adb | 6 | ||||
| -rw-r--r-- | src/vhdl/translate/trans-chap9.adb | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/vhdl/translate/ortho_front.adb b/src/vhdl/translate/ortho_front.adb index 6db015494..2ce7a34a4 100644 --- a/src/vhdl/translate/ortho_front.adb +++ b/src/vhdl/translate/ortho_front.adb @@ -25,7 +25,7 @@ with Interning; with Iirs; use Iirs; with Libraries; with Iirs_Utils; use Iirs_Utils; -with Std_Package; +with Vhdl.Std_Package; with Flags; with Vhdl.Configuration; with Translation; @@ -327,8 +327,8 @@ package body Ortho_Front is Vhdl.Configuration.Flag_Load_All_Design_Units := False; -- Exclude std.standard - Set_Configuration_Mark_Flag (Std_Package.Std_Standard_Unit, True); - Set_Configuration_Done_Flag (Std_Package.Std_Standard_Unit, True); + Set_Configuration_Mark_Flag (Vhdl.Std_Package.Std_Standard_Unit, True); + Set_Configuration_Done_Flag (Vhdl.Std_Package.Std_Standard_Unit, True); Dep_List := Create_Iir_List; diff --git a/src/vhdl/translate/trans-chap9.adb b/src/vhdl/translate/trans-chap9.adb index 0bf153ebf..f4dc4a422 100644 --- a/src/vhdl/translate/trans-chap9.adb +++ b/src/vhdl/translate/trans-chap9.adb @@ -27,7 +27,7 @@ with Nodes_Meta; with PSL.Nodes; with PSL.NFAs; with PSL.NFAs.Utils; -with Ieee.Std_Logic_1164; +with Vhdl.Ieee.Std_Logic_1164; with Trans.Chap1; with Trans.Chap3; with Trans.Chap4; @@ -389,7 +389,7 @@ package body Trans.Chap9 is Res, New_Lit (Get_Ortho_Literal (Bit_1)), Get_Ortho_Type (Boolean_Type_Definition, Mode_Value)); - elsif Rtype = Ieee.Std_Logic_1164.Std_Ulogic_Type then + elsif Rtype = Vhdl.Ieee.Std_Logic_1164.Std_Ulogic_Type then return New_Value (New_Indexed_Element (New_Obj (Ghdl_Std_Ulogic_To_Boolean_Array), |