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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-04 18:20:30 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-04 18:20:30 +0200 |
| commit | 688173587e76ee89b67b0c0aeb93385c0db08b22 (patch) | |
| tree | 5d9fda9535196719ac8a71f90d1a2d62529d42f0 /src/vhdl/simulate | |
| parent | 17ab141656d8a0ba80309ca4d85e65a038c873e0 (diff) | |
| download | ghdl-688173587e76ee89b67b0c0aeb93385c0db08b22.tar.gz ghdl-688173587e76ee89b67b0c0aeb93385c0db08b22.tar.bz2 ghdl-688173587e76ee89b67b0c0aeb93385c0db08b22.zip | |
vhdl: rename Cover_Statement to Cover_Directive.
Diffstat (limited to 'src/vhdl/simulate')
| -rw-r--r-- | src/vhdl/simulate/simul-elaboration.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/simulate/simul-simulation-main.adb | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb index d1c62a2a5..fe89d48c7 100644 --- a/src/vhdl/simulate/simul-elaboration.adb +++ b/src/vhdl/simulate/simul-elaboration.adb @@ -1898,7 +1898,7 @@ package body Simul.Elaboration is | Iir_Kind_Psl_Declaration => null; - when Iir_Kind_Psl_Cover_Statement + when Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Assert_Statement | Iir_Kind_Psl_Endpoint_Declaration => Elaborate_Psl_Directive (Instance, Stmt); diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb index 461aeaad0..5af8acb55 100644 --- a/src/vhdl/simulate/simul-simulation-main.adb +++ b/src/vhdl/simulate/simul-simulation-main.adb @@ -436,7 +436,7 @@ package body Simul.Simulation.Main is if V then Nvec := (others => False); case Get_Kind (E.Stmt) is - when Iir_Kind_Psl_Cover_Statement + when Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Endpoint_Declaration => Nvec (0) := True; when others => @@ -483,7 +483,7 @@ package body Simul.Simulation.Main is (E.Instance, "psl assertion", E.Stmt, "assertion violation", 2); end if; - when Iir_Kind_Psl_Cover_Statement => + when Iir_Kind_Psl_Cover_Directive => if Nvec (S_Num) then if Get_Report_Expression (E.Stmt) /= Null_Iir then Execute_Failed_Assertion @@ -569,7 +569,7 @@ package body Simul.Simulation.Main is (To_Instance_Acc (E'Address), PSL_Assert_Finalizer'Access); end if; - when Iir_Kind_Psl_Cover_Statement => + when Iir_Kind_Psl_Cover_Directive => -- TODO null; when others => |