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| author | Tristan Gingold <tgingold@free.fr> | 2016-02-20 06:48:03 +0100 |
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| committer | Tristan Gingold <tgingold@free.fr> | 2016-02-20 06:51:08 +0100 |
| commit | 002d948aeead104b745e3175e1c684ec7b928847 (patch) | |
| tree | 1b04a8d48bdbc164f4e0998f9eb4e1cc0bfe0930 /src/vhdl/simulate/simulation-main.ads | |
| parent | 49328d94b6bfce72ecc76dc1c9d5c612ebdd2d6c (diff) | |
| download | ghdl-002d948aeead104b745e3175e1c684ec7b928847.tar.gz ghdl-002d948aeead104b745e3175e1c684ec7b928847.tar.bz2 ghdl-002d948aeead104b745e3175e1c684ec7b928847.zip | |
Refactoring in simulate in order to link with ortho.
Diffstat (limited to 'src/vhdl/simulate/simulation-main.ads')
| -rw-r--r-- | src/vhdl/simulate/simulation-main.ads | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/vhdl/simulate/simulation-main.ads b/src/vhdl/simulate/simulation-main.ads new file mode 100644 index 000000000..ed8fe5d69 --- /dev/null +++ b/src/vhdl/simulate/simulation-main.ads @@ -0,0 +1,4 @@ +package Simulation.Main is + -- The entry point of the simulator. + procedure Simulation_Entity (Top_Conf : Iir_Design_Unit); +end Simulation.Main; |