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| author | Tristan Gingold <tgingold@free.fr> | 2021-11-17 18:36:22 +0100 |
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| committer | Tristan Gingold <tgingold@free.fr> | 2021-11-17 18:36:22 +0100 |
| commit | 4e1a1324b8ba4ef83f18742bd4a8588be94735fb (patch) | |
| tree | 603ede0cb1e8d1a84228b3ab09fa173242c1b16a /src/vhdl/simulate/simul-simulation-main.adb | |
| parent | e58c9807fa183b6d1324f9b36ffe1a86bf1f42cb (diff) | |
| download | ghdl-4e1a1324b8ba4ef83f18742bd4a8588be94735fb.tar.gz ghdl-4e1a1324b8ba4ef83f18742bd4a8588be94735fb.tar.bz2 ghdl-4e1a1324b8ba4ef83f18742bd4a8588be94735fb.zip | |
synth: add ports attributes
Diffstat (limited to 'src/vhdl/simulate/simul-simulation-main.adb')
0 files changed, 0 insertions, 0 deletions