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authorTristan Gingold <tgingold@free.fr>2016-03-22 05:34:06 +0100
committerTristan Gingold <tgingold@free.fr>2016-03-22 05:44:49 +0100
commitdb9df06f901abe21976ae8f5d3b680965daef70b (patch)
tree7a5a5d9a2485c9fb0b593dd1f25f5b96defbbb34 /src/vhdl/sem_names.adb
parent89cff67d5cf64c46818043e269c1d9f56a2ac149 (diff)
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PSL: add clocked SERE, make endpoints visible from VHDL.
Diffstat (limited to 'src/vhdl/sem_names.adb')
-rw-r--r--src/vhdl/sem_names.adb6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/vhdl/sem_names.adb b/src/vhdl/sem_names.adb
index a65fd54ef..a4a6b44ca 100644
--- a/src/vhdl/sem_names.adb
+++ b/src/vhdl/sem_names.adb
@@ -1598,7 +1598,8 @@ package body Sem_Names is
return Res;
when Iir_Kind_Psl_Expression =>
return Res;
- when Iir_Kind_Psl_Declaration =>
+ when Iir_Kind_Psl_Declaration
+ | Iir_Kind_Psl_Endpoint_Declaration =>
return Name;
when Iir_Kind_Element_Declaration
| Iir_Kind_Error =>
@@ -2512,7 +2513,8 @@ package body Sem_Names is
(Disp_Node (Prefix) & " cannot be indexed or sliced", Name);
Res := Null_Iir;
- when Iir_Kind_Psl_Declaration =>
+ when Iir_Kind_Psl_Declaration
+ | Iir_Kind_Psl_Endpoint_Declaration =>
Res := Sem_Psl.Sem_Psl_Name (Name);
when Iir_Kinds_Library_Unit_Declaration =>