add synthesis support for logic operators on numeric types (#893)

* add logic operators on unsigned

* handle signed too

* handle unary not

2 files changed, 35 insertions, 4 deletions

diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb
index e7d61b11c..2abd0da44 100644
--- a/src/synth/synth-disp_vhdl.adb
+++ b/src/synth/synth-disp_vhdl.adb
@@ -25,6 +25,7 @@ with Name_Table;
 with Vhdl.Prints;
 with Vhdl.Std_Package;
 with Vhdl.Ieee.Std_Logic_1164;
+with Vhdl.Ieee.Numeric;
 with Vhdl.Errors; use Vhdl.Errors;
 with Vhdl.Utils; use Vhdl.Utils;
 
@@ -101,6 +102,16 @@ package body Synth.Disp_Vhdl is
                end if;
                Put_Line (";");
                Idx := Idx + 1;
+            elsif Btype = Vhdl.Ieee.Numeric.Numeric_Std_Unsigned_Type
+               or Btype = Vhdl.Ieee.Numeric.Numeric_Std_Signed_Type then
+               Put ("  wrap_" & Pfx & " <= std_logic_vector(" & Pfx);
+               if Desc.W = 1 then
+                  --  This is an array of length 1.  A scalar is used in the
+                  --  netlist.
+                  Put (" (" & Pfx & "'left)");
+               end if;
+               Put_Line (");");
+               Idx := Idx + 1;
             else
                Error_Kind ("disp_in_converter(arr)", Ptype);
             end if;
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb
index 592f25297..43a2f4c3b 100644
--- a/src/synth/synth-expr.adb
+++ b/src/synth/synth-expr.adb
@@ -933,12 +933,30 @@ package body Synth.Expr is
            | Iir_Predefined_Ieee_1164_Scalar_Xnor =>
             return Synth_Bit_Dyadic (Id_Xnor);
 
-         when Iir_Predefined_Ieee_1164_Vector_And =>
+         when Iir_Predefined_Ieee_1164_Vector_And
+            | Iir_Predefined_Ieee_Numeric_Std_And_Uns_Uns
+            | Iir_Predefined_Ieee_Numeric_Std_And_Sgn_Sgn =>
             return Synth_Vec_Dyadic (Id_And);
-         when Iir_Predefined_Ieee_1164_Vector_Or =>
+         when Iir_Predefined_Ieee_1164_Vector_Or
+            | Iir_Predefined_Ieee_Numeric_Std_Or_Uns_Uns
+            | Iir_Predefined_Ieee_Numeric_Std_Or_Sgn_Sgn =>
             return Synth_Vec_Dyadic (Id_Or);
-         when Iir_Predefined_Ieee_1164_Vector_Xor =>
+         when Iir_Predefined_Ieee_1164_Vector_Nand
+            | Iir_Predefined_Ieee_Numeric_Std_Nand_Uns_Uns
+            | Iir_Predefined_Ieee_Numeric_Std_Nand_Sgn_Sgn =>
+            return Synth_Vec_Dyadic (Id_Nand);
+         when Iir_Predefined_Ieee_1164_Vector_Nor
+            | Iir_Predefined_Ieee_Numeric_Std_Nor_Uns_Uns
+            | Iir_Predefined_Ieee_Numeric_Std_Nor_Sgn_Sgn =>
+            return Synth_Vec_Dyadic (Id_Nor);
+         when Iir_Predefined_Ieee_1164_Vector_Xor
+            | Iir_Predefined_Ieee_Numeric_Std_Xor_Uns_Uns
+            | Iir_Predefined_Ieee_Numeric_Std_Xor_Sgn_Sgn =>
             return Synth_Vec_Dyadic (Id_Xor);
+         when Iir_Predefined_Ieee_1164_Vector_Xnor
+            | Iir_Predefined_Ieee_Numeric_Std_Xnor_Uns_Uns
+            | Iir_Predefined_Ieee_Numeric_Std_Xnor_Sgn_Sgn =>
+            return Synth_Vec_Dyadic (Id_Xnor);
 
          when Iir_Predefined_Enum_Equality =>
             if Is_Bit_Type (Left_Type) then
@@ -1218,7 +1236,9 @@ package body Synth.Expr is
             return null;
          when Iir_Predefined_Ieee_1164_Scalar_Not =>
             return Synth_Bit_Monadic (Id_Not);
-         when Iir_Predefined_Ieee_1164_Vector_Not =>
+         when Iir_Predefined_Ieee_1164_Vector_Not
+            | Iir_Predefined_Ieee_Numeric_Std_Not_Uns
+            | Iir_Predefined_Ieee_Numeric_Std_Not_Sgn =>
             return Synth_Vec_Monadic (Id_Not);
          when Iir_Predefined_Ieee_Numeric_Std_Neg_Uns
            | Iir_Predefined_Ieee_Numeric_Std_Neg_Sgn =>