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| author | Tristan Gingold <tgingold@free.fr> | 2020-06-18 21:58:54 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-06-18 21:58:54 +0200 |
| commit | efce47b470ef6305b620ff97b3cc689e2d0db10a (patch) | |
| tree | aa7aa9ccdc3b8654fe732b601b77eafd9540c0fe /src/synth | |
| parent | 1666a4c7458a9078daa77058ef6173bf34223018 (diff) | |
| download | ghdl-efce47b470ef6305b620ff97b3cc689e2d0db10a.tar.gz ghdl-efce47b470ef6305b620ff97b3cc689e2d0db10a.tar.bz2 ghdl-efce47b470ef6305b620ff97b3cc689e2d0db10a.zip | |
synth-oper: handle add_uns_int_slv. For ghdl/ghdl-yosys-plugin#126
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/synth-oper.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 3059298f3..b66d0c947 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -869,7 +869,8 @@ package body Synth.Oper is return Synth_Compare_Array (Id_Ult, Boolean_Type); when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat - | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int => + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Int_Slv + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int => -- "+" (Unsigned, Natural) return Synth_Dyadic_Uns_Nat (Ctxt, Id_Add, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Add_Nat_Uns => |