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| author | Tristan Gingold <tgingold@free.fr> | 2020-06-15 19:38:45 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-06-15 19:40:17 +0200 |
| commit | 7d85d728bb261ad70ee7238851989bac0fc9ce47 (patch) | |
| tree | d60fd513615d548235e04a35e7f8e46422947767 /src/synth | |
| parent | 0316f95368837dc163173e7ca52f37ecd8d3591d (diff) | |
| download | ghdl-7d85d728bb261ad70ee7238851989bac0fc9ce47.tar.gz ghdl-7d85d728bb261ad70ee7238851989bac0fc9ce47.tar.bz2 ghdl-7d85d728bb261ad70ee7238851989bac0fc9ce47.zip | |
vhdl: create default configuration for a vunit. Fix #1372
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/synth-insts.adb | 2 | ||||
| -rw-r--r-- | src/synth/synth-stmts.adb | 3 |
2 files changed, 4 insertions, 1 deletions
diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb index da1cc329c..c2bb5d580 100644 --- a/src/synth/synth-insts.adb +++ b/src/synth/synth-insts.adb @@ -1387,7 +1387,7 @@ package body Synth.Insts is pragma Assert (Get_Block_From_Block_Specification (Get_Block_Specification (Cfg)) = Blk); - Clear_Instantiation_Configuration (Blk); + -- Clear_Instantiation_Configuration (Blk); Item := Get_Configuration_Item_Chain (Cfg); while Item /= Null_Node loop diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index cdc5290a4..9418c6e22 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -3628,6 +3628,9 @@ package body Synth.Stmts is Mark (M, Proc_Pool); Instance_Pool := Proc_Pool'Access; + Apply_Block_Configuration + (Get_Verification_Block_Configuration (Unit), Unit); + Last_Type := Null_Node; Item := Get_Vunit_Item_Chain (Unit); while Item /= Null_Node loop |