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| author | Tristan Gingold <tgingold@free.fr> | 2020-04-21 05:46:12 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-04-21 05:46:12 +0200 |
| commit | 5e1607f130ecdd6a228b3329ffc680bd42b486bb (patch) | |
| tree | 115f1da635555fc71d6fa17340e7dcf0422a78f3 /src/synth | |
| parent | de0014ddf3d2920aa7d4a4e8fe9d05ed2eebc4a4 (diff) | |
| download | ghdl-5e1607f130ecdd6a228b3329ffc680bd42b486bb.tar.gz ghdl-5e1607f130ecdd6a228b3329ffc680bd42b486bb.tar.bz2 ghdl-5e1607f130ecdd6a228b3329ffc680bd42b486bb.zip | |
synth-oper: handle more std_logic_arith."+" operations. Fix #1253
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/synth-oper.adb | 36 |
1 files changed, 19 insertions, 17 deletions
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 2ee88c328..12fa0239b 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -843,35 +843,37 @@ package body Synth.Oper is -- "+" (Natural, Unsigned) return Synth_Dyadic_Nat_Uns (Id_Add, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns - | Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log - | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Log - | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Uns - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Slv - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Uns => + | Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Log + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Uns + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Slv + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Uns => -- "+" (Unsigned, Unsigned) return Synth_Dyadic_Uns_Uns (Id_Add, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Int - | Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Int => + | Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Int => -- "+" (Signed, Integer) return Synth_Dyadic_Sgn_Int (Id_Add, Left, Right, Expr); - when Iir_Predefined_Ieee_Numeric_Std_Add_Int_Sgn => + when Iir_Predefined_Ieee_Numeric_Std_Add_Int_Sgn + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Sgn_Sgn + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Sgn_Slv => -- "+" (Integer, Signed) return Synth_Dyadic_Int_Sgn (Id_Add, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Sgn - | Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Log - | Iir_Predefined_Ieee_Numeric_Std_Add_Log_Sgn - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Sgn - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Sgn - | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv - | Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv => + | Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Log + | Iir_Predefined_Ieee_Numeric_Std_Add_Log_Sgn + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Sgn + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Sgn + | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv + | Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv => -- "+" (Signed, Signed) return Synth_Dyadic_Sgn_Sgn (Id_Add, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat - | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int => + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int => -- "-" (Unsigned, Natural) return Synth_Dyadic_Uns_Nat (Id_Sub, Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns |