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authorTristan Gingold <tgingold@free.fr>2019-09-20 18:28:21 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-20 18:28:21 +0200
commit466156df1f0ab01b434c39405fef5eb7ba62f927 (patch)
treea311730ff9499507f757769710ce98fd2c0bfcd6 /src/synth
parent6448431a20876b11744db3e663254ae42c752b74 (diff)
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synth: add base_instance.
Diffstat (limited to 'src/synth')
-rw-r--r--src/synth/synth-context.adb37
-rw-r--r--src/synth/synth-context.ads16
-rw-r--r--src/synth/synth-insts.adb11
-rw-r--r--src/synth/synthesis.adb14
4 files changed, 55 insertions, 23 deletions
diff --git a/src/synth/synth-context.adb b/src/synth/synth-context.adb
index 3a57912f1..ecc36fa75 100644
--- a/src/synth/synth-context.adb
+++ b/src/synth/synth-context.adb
@@ -43,14 +43,22 @@ package body Synth.Context is
function Make_Base_Instance return Synth_Instance_Acc
is
- Global_Module : Module;
+ Base : Base_Instance_Acc;
+ Top_Module : Module;
Res : Synth_Instance_Acc;
begin
- Global_Module :=
+ Top_Module :=
New_Design (New_Sname_Artificial (Get_Identifier ("top")));
- Build_Context := Build_Builders (Global_Module);
+ Build_Context := Build_Builders (Top_Module);
+
+ Base := new Base_Instance_Type'(Builder => Build_Context,
+ Top_Module => Top_Module,
+ Cur_Module => No_Module,
+ Bit0 => No_Net,
+ Bit1 => No_Net);
+
Res := new Synth_Instance_Type'(Max_Objs => Global_Info.Nbr_Objects,
- M => Global_Module,
+ Base => Base,
Name => No_Sname,
Block_Scope => Global_Info,
Up_Block => null,
@@ -76,7 +84,7 @@ package body Synth.Context is
end if;
Res := new Synth_Instance_Type'(Max_Objs => Info.Nbr_Objects,
- M => No_Module,
+ Base => Parent.Base,
Name => Name,
Block_Scope => Scope,
Up_Block => Parent,
@@ -93,16 +101,29 @@ package body Synth.Context is
Deallocate (Synth_Inst);
end Free_Instance;
- procedure Set_Instance_Module (Inst : Synth_Instance_Acc; M : Module) is
+ procedure Set_Instance_Module (Inst : Synth_Instance_Acc; M : Module)
+ is
+ Prev_Base : constant Base_Instance_Acc := Inst.Base;
+ Base : Base_Instance_Acc;
begin
- Inst.M := M;
+ Base := new Base_Instance_Type'(Builder => Prev_Base.Builder,
+ Top_Module => Prev_Base.Top_Module,
+ Cur_Module => M,
+ Bit0 => No_Net,
+ Bit1 => No_Net);
+ Inst.Base := Base;
end Set_Instance_Module;
function Get_Instance_Module (Inst : Synth_Instance_Acc) return Module is
begin
- return Inst.M;
+ return Inst.Base.Cur_Module;
end Get_Instance_Module;
+ function Get_Top_Module (Inst : Synth_Instance_Acc) return Module is
+ begin
+ return Inst.Base.Top_Module;
+ end Get_Top_Module;
+
function Get_Sname (Inst : Synth_Instance_Acc) return Sname is
begin
return Inst.Name;
diff --git a/src/synth/synth-context.ads b/src/synth/synth-context.ads
index 9ea00782c..2b7aaeeab 100644
--- a/src/synth/synth-context.ads
+++ b/src/synth/synth-context.ads
@@ -51,6 +51,8 @@ package Synth.Context is
function Get_Sname (Inst : Synth_Instance_Acc) return Sname;
pragma Inline (Get_Sname);
+ function Get_Top_Module (Inst : Synth_Instance_Acc) return Module;
+
procedure Set_Instance_Module (Inst : Synth_Instance_Acc; M : Module);
function Get_Instance_Module (Inst : Synth_Instance_Acc) return Module;
pragma Inline (Get_Instance_Module);
@@ -91,9 +93,19 @@ package Synth.Context is
private
type Objects_Array is array (Object_Slot_Type range <>) of Value_Acc;
+ type Base_Instance_Type is limited record
+ Builder : Netlists.Builders.Context_Acc;
+ Top_Module : Module;
+
+ Cur_Module : Module;
+ Bit0 : Net;
+ Bit1 : Net;
+ end record;
+
+ type Base_Instance_Acc is access Base_Instance_Type;
+
type Synth_Instance_Type (Max_Objs : Object_Slot_Type) is limited record
- -- Module which owns gates created for this instance.
- M : Module;
+ Base : Base_Instance_Acc;
-- Name prefix for declarations.
Name : Sname;
diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb
index 223245601..2eacb96e3 100644
--- a/src/synth/synth-insts.adb
+++ b/src/synth/synth-insts.adb
@@ -161,6 +161,7 @@ package body Synth.Insts is
Nbr_Inputs : Port_Nbr;
Nbr_Outputs : Port_Nbr;
Num : Uns32;
+ Cur_Module : Module;
begin
if Get_Kind (Params.Decl) = Iir_Kind_Component_Declaration then
pragma Assert (Params.Arch = Null_Node);
@@ -217,10 +218,10 @@ package body Synth.Insts is
end loop;
-- Declare module.
- Set_Instance_Module
- (Syn_Inst, New_User_Module (Get_Instance_Module (Root_Instance),
- New_Sname_User (Get_Identifier (Decl)),
- Id_User_None, Nbr_Inputs, Nbr_Outputs, 0));
+ Cur_Module := New_User_Module (Get_Top_Module (Root_Instance),
+ New_Sname_User (Get_Identifier (Decl)),
+ Id_User_None, Nbr_Inputs, Nbr_Outputs, 0);
+ Set_Instance_Module (Syn_Inst, Cur_Module);
-- Add ports to module.
declare
@@ -244,7 +245,7 @@ package body Synth.Insts is
end loop;
pragma Assert (Nbr_Inputs = Inports'Last);
pragma Assert (Nbr_Outputs = Outports'Last);
- Set_Port_Desc (Get_Instance_Module (Syn_Inst), Inports, Outports);
+ Set_Port_Desc (Cur_Module, Inports, Outports);
end;
return Inst_Object'(Decl => Decl,
diff --git a/src/synth/synthesis.adb b/src/synth/synthesis.adb
index f847105aa..5d41ad70f 100644
--- a/src/synth/synthesis.adb
+++ b/src/synth/synthesis.adb
@@ -109,7 +109,7 @@ package body Synthesis is
Unit : constant Node := Get_Library_Unit (Design);
Arch : Node;
Config : Node;
- Global_Instance : Synth_Instance_Acc;
+ Top_Instance : Synth_Instance_Acc;
begin
-- Extract architecture from design.
case Get_Kind (Unit) is
@@ -125,23 +125,21 @@ package body Synthesis is
Error_Kind ("synth_design", Unit);
end case;
- Global_Instance := Make_Base_Instance;
+ Top_Instance := Make_Base_Instance;
Synth.Values.Init;
Synth.Insts.Init;
-- Dependencies first.
- Synth_Dependencies
- (Global_Instance, Get_Design_Unit (Get_Entity (Arch)));
- Synth_Dependencies
- (Global_Instance, Get_Design_Unit (Arch));
+ Synth_Dependencies (Top_Instance, Get_Design_Unit (Get_Entity (Arch)));
+ Synth_Dependencies (Top_Instance, Get_Design_Unit (Arch));
- Synth_Top_Entity (Global_Instance, Arch, Config, Inst);
+ Synth_Top_Entity (Top_Instance, Arch, Config, Inst);
Synth_All_Instances;
if Errorout.Nbr_Errors > 0 then
raise Compilation_Error;
end if;
- M := Get_Instance_Module (Global_Instance);
+ M := Get_Top_Module (Top_Instance);
end Synth_Design;
end Synthesis;