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| author | Tristan Gingold <tgingold@free.fr> | 2019-09-01 11:03:38 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-09-02 20:40:56 +0200 |
| commit | 0dd21ac4324d3541fc223989205469e2b46d49bf (patch) | |
| tree | a8a0018a65d1998dea5ce3715ec2267741852371 /src/synth | |
| parent | fdd89d0259d35d76c56770c74f6ffee8b5ebf239 (diff) | |
| download | ghdl-0dd21ac4324d3541fc223989205469e2b46d49bf.tar.gz ghdl-0dd21ac4324d3541fc223989205469e2b46d49bf.tar.bz2 ghdl-0dd21ac4324d3541fc223989205469e2b46d49bf.zip | |
synth: handle conditional variable assignment.
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/synth-stmts.adb | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index c36400e91..dc61e4ce9 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -341,6 +341,38 @@ package body Synth.Stmts is Synth_Assignment (Syn_Inst, Target, Val, Stmt); end Synth_Variable_Assignment; + procedure Synth_Conditional_Variable_Assignment + (Syn_Inst : Synth_Instance_Acc; Stmt : Node) + is + Target : constant Node := Get_Target (Stmt); + Targ_Type : constant Node := Get_Type (Target); + Cond : Node; + Ce : Node; + Val, Cond_Val : Value_Acc; + First, Last : Value_Acc; + begin + Last := null; + Ce := Get_Conditional_Expression_Chain (Stmt); + while Ce /= Null_Node loop + Val := Synth_Expression_With_Type + (Syn_Inst, Get_Expression (Ce), Targ_Type); + Cond := Get_Condition (Ce); + if Cond /= Null_Node then + Cond_Val := Synth_Expression (Syn_Inst, Cond); + Val := Create_Value_Mux2 (Cond_Val, Val, null); + end if; + + if Last /= null then + Last.M_F := Val; + else + First := Val; + end if; + Last := Val; + Ce := Get_Chain (Ce); + end loop; + Synth_Assignment (Syn_Inst, Target, First, Stmt); + end Synth_Conditional_Variable_Assignment; + procedure Synth_If_Statement (Syn_Inst : Synth_Instance_Acc; Stmt : Node) is @@ -1216,6 +1248,8 @@ package body Synth.Stmts is Synth_Conditional_Signal_Assignment (Syn_Inst, Stmt); when Iir_Kind_Variable_Assignment_Statement => Synth_Variable_Assignment (Syn_Inst, Stmt); + when Iir_Kind_Conditional_Variable_Assignment_Statement => + Synth_Conditional_Variable_Assignment (Syn_Inst, Stmt); when Iir_Kind_Case_Statement => Synth_Case_Statement (Syn_Inst, Stmt); when Iir_Kind_For_Loop_Statement => |