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author | Tristan Gingold <tgingold@free.fr> | 2021-04-27 06:58:02 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-04-27 21:14:35 +0200 |
commit | 94d4ef5976f9bd15e4253200b0577a7a86e0bc22 (patch) | |
tree | 5ea06b5fcef250fd98efd896e2a6ae5fc7048a21 /src/synth/synth-vhdl_context.adb | |
parent | f5715a802c157614b6cd9ad4f0195ce77cbd0997 (diff) | |
download | ghdl-94d4ef5976f9bd15e4253200b0577a7a86e0bc22.tar.gz ghdl-94d4ef5976f9bd15e4253200b0577a7a86e0bc22.tar.bz2 ghdl-94d4ef5976f9bd15e4253200b0577a7a86e0bc22.zip |
synth: use a generic version of synth-environment.
Diffstat (limited to 'src/synth/synth-vhdl_context.adb')
-rw-r--r-- | src/synth/synth-vhdl_context.adb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/synth/synth-vhdl_context.adb b/src/synth/synth-vhdl_context.adb index 2a497ae0f..0ef9b417e 100644 --- a/src/synth/synth-vhdl_context.adb +++ b/src/synth/synth-vhdl_context.adb @@ -316,7 +316,7 @@ package body Synth.Vhdl_Context is if Kind = Wire_None then Wid := No_Wire_Id; else - Wid := Alloc_Wire (Kind, Otyp, Obj); + Wid := Alloc_Wire (Kind, (Obj, Otyp)); end if; Val := Create_Value_Wire (Wid, Otyp); |