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author | Tristan Gingold <tgingold@free.fr> | 2019-10-15 07:33:05 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-15 07:33:05 +0200 |
commit | d70fe587b2fd10eb8fca337af553a2a65aa434a8 (patch) | |
tree | 13cfaff206d54435745d58c2149b53692f73a676 /src/synth/synth-insts.adb | |
parent | 66335e7a44dc449e99706c26d51f6da11b01a7f7 (diff) | |
download | ghdl-d70fe587b2fd10eb8fca337af553a2a65aa434a8.tar.gz ghdl-d70fe587b2fd10eb8fca337af553a2a65aa434a8.tar.bz2 ghdl-d70fe587b2fd10eb8fca337af553a2a65aa434a8.zip |
synth-insts: accept architecture instantiation in synth_dependencies.
Diffstat (limited to 'src/synth/synth-insts.adb')
-rw-r--r-- | src/synth/synth-insts.adb | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb index 6c0e65864..6315fa342 100644 --- a/src/synth/synth-insts.adb +++ b/src/synth/synth-insts.adb @@ -642,8 +642,9 @@ package body Synth.Insts is Dep_It := List_Iterate (Dep_List); while Is_Valid (Dep_It) loop Dep := Get_Element (Dep_It); - pragma Assert (Get_Kind (Dep) = Iir_Kind_Design_Unit); - if not Get_Elab_Flag (Dep) then + if Get_Kind (Dep) = Iir_Kind_Design_Unit + and then not Get_Elab_Flag (Dep) + then Set_Elab_Flag (Dep, True); Synth_Dependencies (Parent_Inst, Dep); Dep_Unit := Get_Library_Unit (Dep); |