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| author | Tristan Gingold <tgingold@free.fr> | 2019-09-30 20:10:18 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-09-30 20:10:18 +0200 |
| commit | 1e17ca0e0d9fcdc9ba29c82b40c841d87e5b86a3 (patch) | |
| tree | cb135394ce7ce8ceec52a3cc79791e4c72a5f33e /src/synth/synth-insts.adb | |
| parent | 1f62927ba89abc0fd43b1fceaa3c960252b05a26 (diff) | |
| download | ghdl-1e17ca0e0d9fcdc9ba29c82b40c841d87e5b86a3.tar.gz ghdl-1e17ca0e0d9fcdc9ba29c82b40c841d87e5b86a3.tar.bz2 ghdl-1e17ca0e0d9fcdc9ba29c82b40c841d87e5b86a3.zip | |
synth: renaming and minor refactoring.
Diffstat (limited to 'src/synth/synth-insts.adb')
| -rw-r--r-- | src/synth/synth-insts.adb | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb index 656db9e58..cdd917536 100644 --- a/src/synth/synth-insts.adb +++ b/src/synth/synth-insts.adb @@ -178,11 +178,11 @@ package body Synth.Insts is Synth_Declaration_Type (Syn_Inst, Inter); case Mode_To_Port_Kind (Get_Mode (Inter)) is when Port_In => - Make_Object (Syn_Inst, Wire_None, Inter); + Create_Wire_Object (Syn_Inst, Wire_None, Inter); Nbr_Inputs := Nbr_Inputs + 1; when Port_Out | Port_Inout => - Make_Object (Syn_Inst, Wire_None, Inter); + Create_Wire_Object (Syn_Inst, Wire_None, Inter); Nbr_Outputs := Nbr_Outputs + 1; end case; Inter := Get_Chain (Inter); @@ -274,18 +274,20 @@ package body Synth.Insts is case Mode_To_Port_Kind (Get_Mode (Inter)) is when Port_In => - Connect - (Get_Input (Inst, Nbr_Inputs), - Get_Net (Synth_Expression (Syn_Inst, Actual))); + -- Connect the net to the input. + Connect (Get_Input (Inst, Nbr_Inputs), + Get_Net (Synth_Expression (Syn_Inst, Actual))); Nbr_Inputs := Nbr_Inputs + 1; when Port_Out | Port_Inout => if Actual /= Null_Iir then + -- Create a port gate (so that is has a name). Port := Get_Output (Inst, Nbr_Outputs); Port := Builders.Build_Port (Get_Build (Syn_Inst), Port); O := Create_Value_Net (Port, Get_Value_Type (Inst_Obj.Syn_Inst, Get_Type (Inter))); + -- Assign the port output to the actual (a net). Synth_Assignment (Syn_Inst, Actual, O, Assoc); end if; Nbr_Outputs := Nbr_Outputs + 1; @@ -332,10 +334,10 @@ package body Synth.Insts is Synth_Declaration_Type (Sub_Inst, Inter); case Mode_To_Port_Kind (Get_Mode (Inter)) is when Port_In => - Make_Object (Sub_Inst, Wire_None, Inter); + Create_Wire_Object (Sub_Inst, Wire_None, Inter); when Port_Out | Port_Inout => - Make_Object (Sub_Inst, Wire_None, Inter); + Create_Wire_Object (Sub_Inst, Wire_None, Inter); end case; Inter := Get_Chain (Inter); end loop; @@ -480,7 +482,7 @@ package body Synth.Insts is (Syn_Inst, Actual, Inter_Type)); when Port_Out | Port_Inout => - Make_Object (Comp_Inst, Wire_None, Assoc_Inter); + Create_Wire_Object (Comp_Inst, Wire_None, Assoc_Inter); Create_Component_Wire (Assoc_Inter, Get_Value (Comp_Inst, Assoc_Inter)); end case; @@ -621,10 +623,10 @@ package body Synth.Insts is Synth_Declaration_Type (Syn_Inst, Inter); case Mode_To_Port_Kind (Get_Mode (Inter)) is when Port_In => - Make_Object (Syn_Inst, Wire_None, Inter); + Create_Wire_Object (Syn_Inst, Wire_None, Inter); when Port_Out | Port_Inout => - Make_Object (Syn_Inst, Wire_None, Inter); + Create_Wire_Object (Syn_Inst, Wire_None, Inter); end case; Inter := Get_Chain (Inter); end loop; |