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authorTristan Gingold <tgingold@free.fr>2020-04-01 08:19:35 +0200
committerTristan Gingold <tgingold@free.fr>2020-04-01 08:19:35 +0200
commit02efa5de54ddd02dfa03c644c49d8fffba5960bb (patch)
tree8a7f885f8962489de11d11d5d2a62a63824bc9a1 /src/synth/synth-ieee-numeric_std.adb
parentfb2b12d8f190660e9c4f583f9aa50bcf73838a81 (diff)
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synth-static_oper: handle mul nat uns. Fix #1179
Diffstat (limited to 'src/synth/synth-ieee-numeric_std.adb')
-rw-r--r--src/synth/synth-ieee-numeric_std.adb27
1 files changed, 27 insertions, 0 deletions
diff --git a/src/synth/synth-ieee-numeric_std.adb b/src/synth/synth-ieee-numeric_std.adb
index ca0f48362..d997c93b8 100644
--- a/src/synth/synth-ieee-numeric_std.adb
+++ b/src/synth/synth-ieee-numeric_std.adb
@@ -252,6 +252,33 @@ package body Synth.Ieee.Numeric_Std is
return Res;
end Mul_Uns_Uns;
+ procedure To_Unsigned (Res : out Std_Logic_Vector; Val : Uns64)
+ is
+ E : Std_Ulogic;
+ begin
+ for I in Res'Range loop
+ if (Shift_Right (Val, Natural (Res'Last - I)) and 1) = 0 then
+ E := '0';
+ else
+ E := '1';
+ end if;
+ Res (I) := E;
+ end loop;
+ end To_Unsigned;
+
+ function Mul_Nat_Uns (L : Uns64; R : Std_Logic_Vector)
+ return Std_Logic_Vector
+ is
+ pragma Assert (R'First = 1);
+ T : Std_Logic_Vector (1 .. R'Last);
+ begin
+ if R'Last < 1 then
+ return Null_Vec;
+ end if;
+ To_Unsigned (T, L);
+ return Mul_Uns_Uns (T, R);
+ end Mul_Nat_Uns;
+
function Mul_Sgn_Sgn (L, R : Std_Logic_Vector) return Std_Logic_Vector
is
pragma Assert (L'First = 1);