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| author | Tristan Gingold <tgingold@free.fr> | 2019-08-29 06:55:52 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-08-29 06:55:52 +0200 |
| commit | 698c668481e9ca77234317bca7047efd8210c24c (patch) | |
| tree | 2853048fbd75630e90eb2f350ee19aa0517060ba /src/synth/synth-environment.adb | |
| parent | c794aaa2a7dbec514d188c28f75da181a5692992 (diff) | |
| download | ghdl-698c668481e9ca77234317bca7047efd8210c24c.tar.gz ghdl-698c668481e9ca77234317bca7047efd8210c24c.tar.bz2 ghdl-698c668481e9ca77234317bca7047efd8210c24c.zip | |
synth: add support for record types.
(WIP: need to fix regression of stmt01).
Diffstat (limited to 'src/synth/synth-environment.adb')
| -rw-r--r-- | src/synth/synth-environment.adb | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/synth/synth-environment.adb b/src/synth/synth-environment.adb index 1ae10f951..8b236f310 100644 --- a/src/synth/synth-environment.adb +++ b/src/synth/synth-environment.adb @@ -27,10 +27,6 @@ with Vhdl.Nodes; with Vhdl.Errors; use Vhdl.Errors; package body Synth.Environment is - function Get_Current_Assign_Value - (Ctxt : Builders.Context_Acc; Wid : Wire_Id; Off : Uns32; Wd : Width) - return Net; - procedure Set_Wire_Mark (Wid : Wire_Id; Mark : Boolean := True) is begin Wire_Id_Table.Table (Wid).Mark_Flag := Mark; |