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| author | Tristan Gingold <tgingold@free.fr> | 2019-09-19 06:21:53 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-09-19 06:32:17 +0200 |
| commit | b93769c93d695b4dc77199bdab041da50b1fb5ff (patch) | |
| tree | 66186b8e57c53bd7ac5cb3cb1f17c61479a90d3f /src/synth/synth-decls.adb | |
| parent | f659edc23a249a35e78956054afed0fdc256d127 (diff) | |
| download | ghdl-b93769c93d695b4dc77199bdab041da50b1fb5ff.tar.gz ghdl-b93769c93d695b4dc77199bdab041da50b1fb5ff.tar.bz2 ghdl-b93769c93d695b4dc77199bdab041da50b1fb5ff.zip | |
synth: make synth_instance_type private.
Diffstat (limited to 'src/synth/synth-decls.adb')
| -rw-r--r-- | src/synth/synth-decls.adb | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb index eefa30661..f2f7b5d5e 100644 --- a/src/synth/synth-decls.adb +++ b/src/synth/synth-decls.adb @@ -27,7 +27,6 @@ with Vhdl.Errors; use Vhdl.Errors; with Vhdl.Utils; use Vhdl.Utils; with Vhdl.Std_Package; with Vhdl.Ieee.Std_Logic_1164; -with Vhdl.Annotations; use Vhdl.Annotations; with Synth.Values; use Synth.Values; with Synth.Environment; use Synth.Environment; @@ -51,7 +50,7 @@ package body Synth.Decls is when Value_Wire => -- FIXME: get the width directly from the wire ? W := Get_Type_Width (Val.Typ); - Name := New_Sname (Syn_Inst.Name, Get_Identifier (Decl)); + Name := New_Sname (Get_Sname (Syn_Inst), Get_Identifier (Decl)); if Init /= null then Ival := Get_Net (Init); pragma Assert (Get_Width (Ival) = W); @@ -396,7 +395,7 @@ package body Synth.Decls is if First_Decl /= Null_Node then Val := Synth_Expression_With_Type (Syn_Inst, Get_Default_Value (Decl), Get_Type (Decl)); - Syn_Inst.Objects (Get_Info (First_Decl).Slot) := Val; + Create_Object_Force (Syn_Inst, First_Decl, Val); end if; end Synth_Constant_Declaration; |