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authorTristan Gingold <tgingold@free.fr>2019-09-30 00:23:56 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-30 00:23:56 +0200
commit7eb71d12d9fc376926d1960457cdda7e0d54fcb4 (patch)
treef97c169db84ccd0eed4a0e26b17448da8a82bf53 /src/synth/synth-decls.adb
parentdd6c67ac12d1371b4bc7b1a5570f9522d32a647a (diff)
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synth: refactoring of alias (allow alias of anything).
Diffstat (limited to 'src/synth/synth-decls.adb')
-rw-r--r--src/synth/synth-decls.adb6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb
index 57953ce9f..ba6d2d238 100644
--- a/src/synth/synth-decls.adb
+++ b/src/synth/synth-decls.adb
@@ -524,14 +524,14 @@ package body Synth.Decls is
when Iir_Kind_Object_Alias_Declaration =>
Synth_Declaration_Type (Syn_Inst, Decl);
declare
- Wid : Wire_Id;
+ Obj : Value_Acc;
Off : Uns32;
Typ : Type_Acc;
begin
Stmts.Synth_Assignment_Prefix (Syn_Inst, Get_Name (Decl),
- Wid, Off, Typ);
+ Obj, Off, Typ);
Create_Object (Syn_Inst, Decl,
- Create_Value_Alias (Wid, Off, Typ));
+ Create_Value_Alias (Obj, Off, Typ));
end;
when Iir_Kind_Anonymous_Signal_Declaration =>
Make_Object (Syn_Inst, Wire_Signal, Decl);