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author | Tristan Gingold <tgingold@free.fr> | 2019-05-05 07:49:25 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-05-05 08:05:11 +0200 |
commit | 85d360929d13e6b0bcb082f144883a43f402ce22 (patch) | |
tree | f8d8135e12393588b7704318f26304dfab272658 /src/synth/synth-context.adb | |
parent | 3c48cc2a70085eef63718e622b3d1a7b75a2f36f (diff) | |
download | ghdl-85d360929d13e6b0bcb082f144883a43f402ce22.tar.gz ghdl-85d360929d13e6b0bcb082f144883a43f402ce22.tar.bz2 ghdl-85d360929d13e6b0bcb082f144883a43f402ce22.zip |
vhdl: move std_standard package to vhdl child.
Diffstat (limited to 'src/synth/synth-context.adb')
-rw-r--r-- | src/synth/synth-context.adb | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/synth/synth-context.adb b/src/synth/synth-context.adb index 96242ee73..607c94555 100644 --- a/src/synth/synth-context.adb +++ b/src/synth/synth-context.adb @@ -25,7 +25,7 @@ with Grt.Types; use Grt.Types; with Errorout; use Errorout; with Iirs_Utils; -with Std_Package; +with Vhdl.Std_Package; with Ieee.Std_Logic_1164; with Simul.Annotations; use Simul.Annotations; @@ -139,8 +139,9 @@ package body Synth.Context is case Val.Lit.Kind is when Iir_Value_B1 => pragma Assert - (Val.Lit_Type = Std_Package.Boolean_Type_Definition - or else Val.Lit_Type = Std_Package.Bit_Type_Definition); + (Val.Lit_Type = Vhdl.Std_Package.Boolean_Type_Definition + or else + Val.Lit_Type = Vhdl.Std_Package.Bit_Type_Definition); return Build_Const_UB32 (Build_Context, Ghdl_B1'Pos (Val.Lit.B1), 1); when Iir_Value_E8 => |