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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-02 20:54:44 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-02 20:54:44 +0200 |
| commit | a32cb8c1bd250ec645ec8d392f31cfcc70b9ac76 (patch) | |
| tree | a72277dc5e93feecb9c0e8f140f769a2edcdeb33 /src/synth/netlists-disp_vhdl.adb | |
| parent | 5326b13651c2588c76e87a0b3086d2ab0d6fb0d0 (diff) | |
| download | ghdl-a32cb8c1bd250ec645ec8d392f31cfcc70b9ac76.tar.gz ghdl-a32cb8c1bd250ec645ec8d392f31cfcc70b9ac76.tar.bz2 ghdl-a32cb8c1bd250ec645ec8d392f31cfcc70b9ac76.zip | |
synth: simplify dyn_insert.
Diffstat (limited to 'src/synth/netlists-disp_vhdl.adb')
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index b0fd454a1..353f14475 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -623,7 +623,7 @@ package body Netlists.Disp_Vhdl is when Id_Dyn_Insert => declare -- I0: Input, I1: Value, I2: position - -- P0: Step, P1: offset + -- P0: offset I0 : constant Net := Get_Input_Net (Inst, 0); I1 : constant Net := Get_Input_Net (Inst, 1); I2 : constant Net := Get_Input_Net (Inst, 2); @@ -652,12 +652,12 @@ package body Netlists.Disp_Vhdl is Inst); if Iw > 1 then Disp_Template - ("to_integer (\ui2) * \p0 + (\sp1 + \n0)" & NL & + ("to_integer (\ui2) + (\sp0 + \n0)" & NL & " downto ", Inst, (0 => Iw - 1)); end if; Disp_Template - ("to_integer (\ui2) * \p0 + (\sp1))" & + ("to_integer (\ui2) + (\sp0))" & " <= \i1;" & NL & " end process;" & NL, Inst); |