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| author | Anton Blanchard <anton@ozlabs.org> | 2020-01-12 02:31:50 +1100 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2020-01-11 16:31:50 +0100 |
| commit | 3b0b2e79c310a0fff191036b3be5e15f9ae2e714 (patch) | |
| tree | fa8f3be57c1c151dd0ac7794eaebde67f8fb5a04 /src/synth/netlists-disp_vhdl.adb | |
| parent | 1faca5ed87b2af511ccc055b060a7c6509dda260 (diff) | |
| download | ghdl-3b0b2e79c310a0fff191036b3be5e15f9ae2e714.tar.gz ghdl-3b0b2e79c310a0fff191036b3be5e15f9ae2e714.tar.bz2 ghdl-3b0b2e79c310a0fff191036b3be5e15f9ae2e714.zip | |
netlists: Handle sdiv and udiv (#1082)
Diffstat (limited to 'src/synth/netlists-disp_vhdl.adb')
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 41c32eeaa..2348f669b 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -940,6 +940,12 @@ package body Netlists.Disp_Vhdl is when Id_Srem => Disp_Template (" \o0 <= std_logic_vector (\si0 rem \si1);" & NL, Inst); + when Id_Sdiv => + Disp_Template + (" \o0 <= std_logic_vector (\si0 / \si1);" & NL, Inst); + when Id_Udiv => + Disp_Template + (" \o0 <= std_logic_vector (\ui0 / \ui1);" & NL, Inst); when Id_Lsl => Disp_Template (" \o0 <= std_logic_vector " |