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authorTristan Gingold <tgingold@free.fr>2022-05-11 05:21:40 +0200
committerTristan Gingold <tgingold@free.fr>2022-05-11 05:21:40 +0200
commitfe2afd6a3dd1a9a1234ca095fd63d0e8c999a4d7 (patch)
treea6138c037a8c16f8dae637ff94b2dd9400377ce8 /src/synth/elab-vhdl_insts.adb
parent0a81d6f1ec4106a8e8c90fe455269382e87cc48d (diff)
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synth: add a flag to force creation of variables
Diffstat (limited to 'src/synth/elab-vhdl_insts.adb')
-rw-r--r--src/synth/elab-vhdl_insts.adb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/synth/elab-vhdl_insts.adb b/src/synth/elab-vhdl_insts.adb
index d02691de0..820e20ff1 100644
--- a/src/synth/elab-vhdl_insts.adb
+++ b/src/synth/elab-vhdl_insts.adb
@@ -418,7 +418,7 @@ package body Elab.Vhdl_Insts is
| Iir_Kind_Subtype_Declaration
| Iir_Kind_Type_Declaration
| Iir_Kind_Anonymous_Type_Declaration =>
- Elab_Declaration (Unit_Inst, Item, Last_Type);
+ Elab_Declaration (Unit_Inst, Item, False, Last_Type);
when Iir_Kinds_Concurrent_Signal_Assignment
| Iir_Kinds_Process_Statement
| Iir_Kinds_Generate_Statement