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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-30 18:39:06 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-30 18:39:06 +0100 |
| commit | beadc8e7be3d5d58f6b76d405673642c58b23a30 (patch) | |
| tree | 05f462afc62e5ee29a06213783aa8c34cb12af6b /src/std_names.adb | |
| parent | 500c7cf4c7d307cb51c309e6ebc9c5285e7c5f97 (diff) | |
| download | ghdl-beadc8e7be3d5d58f6b76d405673642c58b23a30.tar.gz ghdl-beadc8e7be3d5d58f6b76d405673642c58b23a30.tar.bz2 ghdl-beadc8e7be3d5d58f6b76d405673642c58b23a30.zip | |
Add names for formal input gates/attributes.
Diffstat (limited to 'src/std_names.adb')
| -rw-r--r-- | src/std_names.adb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/std_names.adb b/src/std_names.adb index d4722240c..aba33a9f6 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -654,6 +654,11 @@ package body Std_Names is Def ("ceil", Name_Ceil); Def ("log2", Name_Log2); + Def ("allconst", Name_Allconst); + Def ("allseq", Name_Allseq); + Def ("anyconst", Name_Anyconst); + Def ("anyseq", Name_Anyseq); + -- Verilog directives Def ("define", Name_Define); Def ("endif", Name_Endif); |