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| author | Tristan Gingold <tgingold@free.fr> | 2019-06-20 08:33:42 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-06-20 08:33:42 +0200 |
| commit | 76f0c844d07a3b0bdefed6aa066c2ab7fc2cf871 (patch) | |
| tree | c8fbe5a60b416145b02345471c2c5383678f8eed /src/std_names.adb | |
| parent | 401f8d3bb30e9c2b2a614ce31370faf870474ed7 (diff) | |
| download | ghdl-76f0c844d07a3b0bdefed6aa066c2ab7fc2cf871.tar.gz ghdl-76f0c844d07a3b0bdefed6aa066c2ab7fc2cf871.tar.bz2 ghdl-76f0c844d07a3b0bdefed6aa066c2ab7fc2cf871.zip | |
vhdl: recognize to_integer/to_signed/to_unsigned.
Diffstat (limited to 'src/std_names.adb')
| -rw-r--r-- | src/std_names.adb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/std_names.adb b/src/std_names.adb index 7628e6407..f19556bc1 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -622,6 +622,9 @@ package body Std_Names is Def ("std_logic_signed", Name_Std_Logic_Signed); Def ("std_logic_textio", Name_Std_Logic_Textio); Def ("std_logic_unsigned", Name_Std_Logic_Unsigned); + Def ("to_integer", Name_To_Integer); + Def ("to_unsigned", Name_To_Unsigned); + Def ("to_signed", Name_To_Signed); -- Verilog directives Def ("define", Name_Define); |